mirror of https://gitlab.com/basile.b/dexed.git
push latest gdb commander changes to fix 32bit build
This commit is contained in:
Basile Burg
parent
2699a0a2d5
commit
7131f5b956
178
src/ce_gdb.pas
178
src/ce_gdb.pas
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@ -8,7 +8,7 @@ uses
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Classes, SysUtils, FileUtil, ListFilterEdit, Forms, Controls, Graphics, RegExpr,
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Classes, SysUtils, FileUtil, ListFilterEdit, Forms, Controls, Graphics, RegExpr,
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ComCtrls, PropEdits, GraphPropEdits, RTTIGrids, Dialogs, ExtCtrls, Menus, strutils,
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ComCtrls, PropEdits, GraphPropEdits, RTTIGrids, Dialogs, ExtCtrls, Menus, strutils,
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Buttons, StdCtrls, process ,ce_common, ce_interfaces, ce_widget, ce_processes,
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Buttons, StdCtrls, process ,ce_common, ce_interfaces, ce_widget, ce_processes,
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ce_observer, ce_synmemo, ce_sharedres;
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ce_observer, ce_synmemo, ce_sharedres, ce_stringrange;
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type
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type
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@ -20,11 +20,11 @@ type
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{$ENDIF}
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{$ENDIF}
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{$IFDEF CPU32}
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{$IFDEF CPU32}
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TCpuRegs = (eax, ebx, ecx, edx, esi, edi, ebp, esp, eip);
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TCpuRegister = (eax, ebx, ecx, edx, esi, edi, ebp, esp, eip);
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{$ENDIF}
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{$ENDIF}
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TFLAG = (F_ID, F_VIP, F_VIF, F_AC, F_VM, F_RF, F_NT, F_IOPL, F_OF, F_DF, F_IF,
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TFLAG = (CS, PF, AF, ZF, SF, TF, IF_, DF, OF_, NT, RF, VM,
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F_TF, F_SF, F_ZF, F_AF, F_PF, F_CF);
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AC, VIF, VIP, ID);
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TEFLAG = set of TFLAG;
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TEFLAG = set of TFLAG;
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TSegmentRegister = (S_CS, S_SS, S_DS, S_ES, S_FS, S_GS);
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TSegmentRegister = (S_CS, S_SS, S_DS, S_ES, S_FS, S_GS);
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@ -277,67 +277,127 @@ var
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str: string;
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str: string;
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reg: string;
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reg: string;
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val: string;
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val: string;
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rng: TStringRange = (ptr: nil; pos: 0; len: 0);
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begin
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begin
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rdr := TStringList.Create;
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try
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setLength(str, stream.Size);
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rdr.LoadFromStream(stream);
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stream.Read(str[1], str.length);
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if (rdr.Count = 0) or (pos('(gdb)', rdr[0]) = -1) then
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rng.init(str);
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if rng.empty then
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exit;
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if not rng.startsWith('&"info registers\n"') then
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exit;
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rng.popUntil(#10)^.popFront;
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while not rng.empty do
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begin
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if rng.front <> '~' then
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exit;
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exit;
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// fix first line
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rng.popFront;
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str := rdr[0];
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if rng.front <> '"' then
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rdr[0] := str[7 .. str.length];
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exit;
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// each line = reg hex dec
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rng.popFront;
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for str in rdr do
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reg := rng.takeUntil([' ', #9]).yield;
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if (reg = 'rip') or (reg = 'eip') then
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begin
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begin
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reg := '';
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rng.popUntil(#10)^.popFront;
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if fWordSpliter.Exec(str) then
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rng.popUntil(#10)^.popFront;
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continue;
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end;
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rng.popUntil(#10)^.popFront;
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if rng.front <> '~' then
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exit;
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rng.popFront;
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if rng.front <> '"' then
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exit;
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rng.popFront;
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if rng.front <> '\' then
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exit;
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rng.popFront;
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if rng.front <> 't' then
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exit;
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rng.popFront;
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if reg = 'eflags' then
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begin
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fFlags := [];
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if rng.front <> '[' then
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exit;
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rng.popFront;
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while rng.front <> ']' do
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begin
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begin
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reg := fWordSpliter.Match[0];
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val := rng.popWhile([' ', #9])^.takeUntil([' ', #9, ']']).yield;
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if fWordSpliter.ExecNext and fWordSpliter.ExecNext then
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case val of
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begin
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'CS': include(fFlags, TFLAG.CS);
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val := fWordSpliter.Match[0];
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'PF': include(fFlags, TFLAG.PF);
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case reg of
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'AF': include(fFlags, TFLAG.AF);
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'cs': fSegment[TSegmentRegister.S_CS] := StrToInt(val);
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'ZF': include(fFlags, TFLAG.ZF);
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'ds': fSegment[TSegmentRegister.S_DS] := StrToInt(val);
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'SF': include(fFlags, TFLAG.SF);
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'es': fSegment[TSegmentRegister.S_ES] := StrToInt(val);
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'TF': include(fFlags, TFLAG.TF);
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'fs': fSegment[TSegmentRegister.S_FS] := StrToInt(val);
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'IF': include(fFlags, TFLAG.IF_);
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'gs': fSegment[TSegmentRegister.S_GS] := StrToInt(val);
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'DF': include(fFlags, TFLAG.DF);
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'ss': fSegment[TSegmentRegister.S_SS] := StrToInt(val);
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'OF': include(fFlags, TFLAG.OF_);
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{$IFDEF CPU64}
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//'NT': include(fFlags, TFLAG.NT);
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'rax': fRegisters[TCpuRegister.rax] := StrToInt64(val);
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//'RF': include(fFlags, TFLAG.RF);
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'rbx': fRegisters[TCpuRegister.rbx] := StrToInt64(val);
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//'VM': include(fFlags, TFLAG.VM);
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'rcx': fRegisters[TCpuRegister.rcx] := StrToInt64(val);
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//'AC': include(fFlags, TFLAG.AC);
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'rdx': fRegisters[TCpuRegister.rdx] := StrToInt64(val);
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//'VIF':include(fFlags, TFLAG.VIF);
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'rdi': fRegisters[TCpuRegister.rdi] := StrToInt64(val);
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//'VIP':include(fFlags, TFLAG.VIP);
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'rsi': fRegisters[TCpuRegister.rsi] := StrToInt64(val);
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//'ID': include(fFlags, TFLAG.ID);
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'rbp': fRegisters[TCpuRegister.rbp] := StrToInt64(val);
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'rsp': fRegisters[TCpuRegister.rsp] := StrToInt64(val);
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'r8': fRegisters[TCpuRegister.r8] := StrToInt64(val);
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'r9': fRegisters[TCpuRegister.r9] := StrToInt64(val);
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'r10': fRegisters[TCpuRegister.r10] := StrToInt64(val);
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'r11': fRegisters[TCpuRegister.r11] := StrToInt64(val);
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'r12': fRegisters[TCpuRegister.r12] := StrToInt64(val);
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'r13': fRegisters[TCpuRegister.r13] := StrToInt64(val);
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'r14': fRegisters[TCpuRegister.r14] := StrToInt64(val);
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'r15': fRegisters[TCpuRegister.r15] := StrToInt64(val);
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'rip': fRegisters[TCpuRegister.rip] := StrToInt64(val);
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{$ELSE}
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'eax': fRegisters[TCpuRegister.eax] := StrToInt(val);
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'ebx': fRegisters[TCpuRegister.ebx] := StrToInt(val);
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'ecx': fRegisters[TCpuRegister.ecx] := StrToInt(val);
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'edx': fRegisters[TCpuRegister.edx] := StrToInt(val);
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'edi': fRegisters[TCpuRegister.edi] := StrToInt(val);
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'esi': fRegisters[TCpuRegister.esi] := StrToInt(val);
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'ebp': fRegisters[TCpuRegister.ebp] := StrToInt(val);
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'esp': fRegisters[TCpuRegister.esp] := StrToInt(val);
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'eip': fRegisters[TCpuRegister.eip] := StrToInt(val);
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{$ENDIF}
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end;
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end;
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end;
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end;
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end;
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rng.popUntil(#10)^.popFront;
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rng.popUntil(#10)^.popFront;
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continue;
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end;
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end;
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finally
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rdr.free;
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val := rng.takeWhile(['0','1','2','3','4','5','6','7','8','9']).yield;
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rng.popUntil(#10)^.popFront;
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rng.popUntil(#10)^.popFront;
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case reg of
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'cs': fSegment[TSegmentRegister.S_CS] := StrToInt(val);
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'ds': fSegment[TSegmentRegister.S_DS] := StrToInt(val);
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'es': fSegment[TSegmentRegister.S_ES] := StrToInt(val);
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'fs': fSegment[TSegmentRegister.S_FS] := StrToInt(val);
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'gs': fSegment[TSegmentRegister.S_GS] := StrToInt(val);
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'ss': fSegment[TSegmentRegister.S_SS] := StrToInt(val);
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{$IFDEF CPU64}
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'rax': fRegisters[TCpuRegister.rax] := StrToInt64(val);
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'rbx': fRegisters[TCpuRegister.rbx] := StrToInt64(val);
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'rcx': fRegisters[TCpuRegister.rcx] := StrToInt64(val);
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'rdx': fRegisters[TCpuRegister.rdx] := StrToInt64(val);
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'rdi': fRegisters[TCpuRegister.rdi] := StrToInt64(val);
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'rsi': fRegisters[TCpuRegister.rsi] := StrToInt64(val);
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'rbp': fRegisters[TCpuRegister.rbp] := StrToInt64(val);
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'rsp': fRegisters[TCpuRegister.rsp] := StrToInt64(val);
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'r8': fRegisters[TCpuRegister.r8] := StrToInt64(val);
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'r9': fRegisters[TCpuRegister.r9] := StrToInt64(val);
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'r10': fRegisters[TCpuRegister.r10] := StrToInt64(val);
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'r11': fRegisters[TCpuRegister.r11] := StrToInt64(val);
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'r12': fRegisters[TCpuRegister.r12] := StrToInt64(val);
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'r13': fRegisters[TCpuRegister.r13] := StrToInt64(val);
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'r14': fRegisters[TCpuRegister.r14] := StrToInt64(val);
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'r15': fRegisters[TCpuRegister.r15] := StrToInt64(val);
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'rip': fRegisters[TCpuRegister.rip] := StrToInt64(val);
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{$ELSE}
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'eax': fRegisters[TCpuRegister.eax] := StrToInt(val);
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'ebx': fRegisters[TCpuRegister.ebx] := StrToInt(val);
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'ecx': fRegisters[TCpuRegister.ecx] := StrToInt(val);
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'edx': fRegisters[TCpuRegister.edx] := StrToInt(val);
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'edi': fRegisters[TCpuRegister.edi] := StrToInt(val);
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'esi': fRegisters[TCpuRegister.esi] := StrToInt(val);
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'ebp': fRegisters[TCpuRegister.ebp] := StrToInt(val);
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'esp': fRegisters[TCpuRegister.esp] := StrToInt(val);
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'eip': fRegisters[TCpuRegister.eip] := StrToInt(val);
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{$ENDIF}
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end;
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end;
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end;
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end;
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end;
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{$ENDREGION}
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{$ENDREGION}
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@ -494,7 +554,7 @@ begin
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fGdb.Executable:= 'gdb' + exeExt;
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fGdb.Executable:= 'gdb' + exeExt;
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fgdb.Options:= [poUsePipes, poStderrToOutPut];
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fgdb.Options:= [poUsePipes, poStderrToOutPut];
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fgdb.Parameters.Add(str);
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fgdb.Parameters.Add(str);
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//fgdb.Parameters.Add('--interpreter=mi');
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fgdb.Parameters.Add('--interpreter=mi');
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fGdb.OnReadData:= @gdbOutput;
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fGdb.OnReadData:= @gdbOutput;
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fGdb.OnTerminate:= @gdbOutput;
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fGdb.OnTerminate:= @gdbOutput;
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fgdb.execute;
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fgdb.execute;
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