From 7131f5b95670e958a20d171572c3f748e830a85a Mon Sep 17 00:00:00 2001 From: Basile Burg Date: Sun, 27 Mar 2016 18:55:24 +0200 Subject: [PATCH] push latest gdb commander changes to fix 32bit build --- src/ce_gdb.pas | 178 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 119 insertions(+), 59 deletions(-) diff --git a/src/ce_gdb.pas b/src/ce_gdb.pas index 53fe5ecc..d83189fb 100644 --- a/src/ce_gdb.pas +++ b/src/ce_gdb.pas @@ -8,7 +8,7 @@ uses Classes, SysUtils, FileUtil, ListFilterEdit, Forms, Controls, Graphics, RegExpr, ComCtrls, PropEdits, GraphPropEdits, RTTIGrids, Dialogs, ExtCtrls, Menus, strutils, Buttons, StdCtrls, process ,ce_common, ce_interfaces, ce_widget, ce_processes, - ce_observer, ce_synmemo, ce_sharedres; + ce_observer, ce_synmemo, ce_sharedres, ce_stringrange; type @@ -20,11 +20,11 @@ type {$ENDIF} {$IFDEF CPU32} - TCpuRegs = (eax, ebx, ecx, edx, esi, edi, ebp, esp, eip); + TCpuRegister = (eax, ebx, ecx, edx, esi, edi, ebp, esp, eip); {$ENDIF} - TFLAG = (F_ID, F_VIP, F_VIF, F_AC, F_VM, F_RF, F_NT, F_IOPL, F_OF, F_DF, F_IF, - F_TF, F_SF, F_ZF, F_AF, F_PF, F_CF); + TFLAG = (CS, PF, AF, ZF, SF, TF, IF_, DF, OF_, NT, RF, VM, + AC, VIF, VIP, ID); TEFLAG = set of TFLAG; TSegmentRegister = (S_CS, S_SS, S_DS, S_ES, S_FS, S_GS); @@ -277,67 +277,127 @@ var str: string; reg: string; val: string; + rng: TStringRange = (ptr: nil; pos: 0; len: 0); begin - rdr := TStringList.Create; - try - rdr.LoadFromStream(stream); - if (rdr.Count = 0) or (pos('(gdb)', rdr[0]) = -1) then + + setLength(str, stream.Size); + stream.Read(str[1], str.length); + rng.init(str); + + if rng.empty then + exit; + if not rng.startsWith('&"info registers\n"') then + exit; + rng.popUntil(#10)^.popFront; + + while not rng.empty do + begin + if rng.front <> '~' then exit; - // fix first line - str := rdr[0]; - rdr[0] := str[7 .. str.length]; - // each line = reg hex dec - for str in rdr do + rng.popFront; + if rng.front <> '"' then + exit; + rng.popFront; + + reg := rng.takeUntil([' ', #9]).yield; + + if (reg = 'rip') or (reg = 'eip') then begin - reg := ''; - if fWordSpliter.Exec(str) then + rng.popUntil(#10)^.popFront; + rng.popUntil(#10)^.popFront; + continue; + end; + + rng.popUntil(#10)^.popFront; + if rng.front <> '~' then + exit; + rng.popFront; + if rng.front <> '"' then + exit; + rng.popFront; + if rng.front <> '\' then + exit; + rng.popFront; + + if rng.front <> 't' then + exit; + rng.popFront; + + + if reg = 'eflags' then + begin + fFlags := []; + if rng.front <> '[' then + exit; + rng.popFront; + while rng.front <> ']' do begin - reg := fWordSpliter.Match[0]; - if fWordSpliter.ExecNext and fWordSpliter.ExecNext then - begin - val := fWordSpliter.Match[0]; - case reg of - 'cs': fSegment[TSegmentRegister.S_CS] := StrToInt(val); - 'ds': fSegment[TSegmentRegister.S_DS] := StrToInt(val); - 'es': fSegment[TSegmentRegister.S_ES] := StrToInt(val); - 'fs': fSegment[TSegmentRegister.S_FS] := StrToInt(val); - 'gs': fSegment[TSegmentRegister.S_GS] := StrToInt(val); - 'ss': fSegment[TSegmentRegister.S_SS] := StrToInt(val); - {$IFDEF CPU64} - 'rax': fRegisters[TCpuRegister.rax] := StrToInt64(val); - 'rbx': fRegisters[TCpuRegister.rbx] := StrToInt64(val); - 'rcx': fRegisters[TCpuRegister.rcx] := StrToInt64(val); - 'rdx': fRegisters[TCpuRegister.rdx] := StrToInt64(val); - 'rdi': fRegisters[TCpuRegister.rdi] := StrToInt64(val); - 'rsi': fRegisters[TCpuRegister.rsi] := StrToInt64(val); - 'rbp': fRegisters[TCpuRegister.rbp] := StrToInt64(val); - 'rsp': fRegisters[TCpuRegister.rsp] := StrToInt64(val); - 'r8': fRegisters[TCpuRegister.r8] := StrToInt64(val); - 'r9': fRegisters[TCpuRegister.r9] := StrToInt64(val); - 'r10': fRegisters[TCpuRegister.r10] := StrToInt64(val); - 'r11': fRegisters[TCpuRegister.r11] := StrToInt64(val); - 'r12': fRegisters[TCpuRegister.r12] := StrToInt64(val); - 'r13': fRegisters[TCpuRegister.r13] := StrToInt64(val); - 'r14': fRegisters[TCpuRegister.r14] := StrToInt64(val); - 'r15': fRegisters[TCpuRegister.r15] := StrToInt64(val); - 'rip': fRegisters[TCpuRegister.rip] := StrToInt64(val); - {$ELSE} - 'eax': fRegisters[TCpuRegister.eax] := StrToInt(val); - 'ebx': fRegisters[TCpuRegister.ebx] := StrToInt(val); - 'ecx': fRegisters[TCpuRegister.ecx] := StrToInt(val); - 'edx': fRegisters[TCpuRegister.edx] := StrToInt(val); - 'edi': fRegisters[TCpuRegister.edi] := StrToInt(val); - 'esi': fRegisters[TCpuRegister.esi] := StrToInt(val); - 'ebp': fRegisters[TCpuRegister.ebp] := StrToInt(val); - 'esp': fRegisters[TCpuRegister.esp] := StrToInt(val); - 'eip': fRegisters[TCpuRegister.eip] := StrToInt(val); - {$ENDIF} - end; + val := rng.popWhile([' ', #9])^.takeUntil([' ', #9, ']']).yield; + case val of + 'CS': include(fFlags, TFLAG.CS); + 'PF': include(fFlags, TFLAG.PF); + 'AF': include(fFlags, TFLAG.AF); + 'ZF': include(fFlags, TFLAG.ZF); + 'SF': include(fFlags, TFLAG.SF); + 'TF': include(fFlags, TFLAG.TF); + 'IF': include(fFlags, TFLAG.IF_); + 'DF': include(fFlags, TFLAG.DF); + 'OF': include(fFlags, TFLAG.OF_); + //'NT': include(fFlags, TFLAG.NT); + //'RF': include(fFlags, TFLAG.RF); + //'VM': include(fFlags, TFLAG.VM); + //'AC': include(fFlags, TFLAG.AC); + //'VIF':include(fFlags, TFLAG.VIF); + //'VIP':include(fFlags, TFLAG.VIP); + //'ID': include(fFlags, TFLAG.ID); end; end; + rng.popUntil(#10)^.popFront; + rng.popUntil(#10)^.popFront; + continue; end; - finally - rdr.free; + + val := rng.takeWhile(['0','1','2','3','4','5','6','7','8','9']).yield; + rng.popUntil(#10)^.popFront; + rng.popUntil(#10)^.popFront; + case reg of + 'cs': fSegment[TSegmentRegister.S_CS] := StrToInt(val); + 'ds': fSegment[TSegmentRegister.S_DS] := StrToInt(val); + 'es': fSegment[TSegmentRegister.S_ES] := StrToInt(val); + 'fs': fSegment[TSegmentRegister.S_FS] := StrToInt(val); + 'gs': fSegment[TSegmentRegister.S_GS] := StrToInt(val); + 'ss': fSegment[TSegmentRegister.S_SS] := StrToInt(val); + {$IFDEF CPU64} + 'rax': fRegisters[TCpuRegister.rax] := StrToInt64(val); + 'rbx': fRegisters[TCpuRegister.rbx] := StrToInt64(val); + 'rcx': fRegisters[TCpuRegister.rcx] := StrToInt64(val); + 'rdx': fRegisters[TCpuRegister.rdx] := StrToInt64(val); + 'rdi': fRegisters[TCpuRegister.rdi] := StrToInt64(val); + 'rsi': fRegisters[TCpuRegister.rsi] := StrToInt64(val); + 'rbp': fRegisters[TCpuRegister.rbp] := StrToInt64(val); + 'rsp': fRegisters[TCpuRegister.rsp] := StrToInt64(val); + 'r8': fRegisters[TCpuRegister.r8] := StrToInt64(val); + 'r9': fRegisters[TCpuRegister.r9] := StrToInt64(val); + 'r10': fRegisters[TCpuRegister.r10] := StrToInt64(val); + 'r11': fRegisters[TCpuRegister.r11] := StrToInt64(val); + 'r12': fRegisters[TCpuRegister.r12] := StrToInt64(val); + 'r13': fRegisters[TCpuRegister.r13] := StrToInt64(val); + 'r14': fRegisters[TCpuRegister.r14] := StrToInt64(val); + 'r15': fRegisters[TCpuRegister.r15] := StrToInt64(val); + 'rip': fRegisters[TCpuRegister.rip] := StrToInt64(val); + {$ELSE} + 'eax': fRegisters[TCpuRegister.eax] := StrToInt(val); + 'ebx': fRegisters[TCpuRegister.ebx] := StrToInt(val); + 'ecx': fRegisters[TCpuRegister.ecx] := StrToInt(val); + 'edx': fRegisters[TCpuRegister.edx] := StrToInt(val); + 'edi': fRegisters[TCpuRegister.edi] := StrToInt(val); + 'esi': fRegisters[TCpuRegister.esi] := StrToInt(val); + 'ebp': fRegisters[TCpuRegister.ebp] := StrToInt(val); + 'esp': fRegisters[TCpuRegister.esp] := StrToInt(val); + 'eip': fRegisters[TCpuRegister.eip] := StrToInt(val); + {$ENDIF} + end; + end; end; {$ENDREGION} @@ -494,7 +554,7 @@ begin fGdb.Executable:= 'gdb' + exeExt; fgdb.Options:= [poUsePipes, poStderrToOutPut]; fgdb.Parameters.Add(str); - //fgdb.Parameters.Add('--interpreter=mi'); + fgdb.Parameters.Add('--interpreter=mi'); fGdb.OnReadData:= @gdbOutput; fGdb.OnTerminate:= @gdbOutput; fgdb.execute;