mirror of
https://github.com/dlang/phobos.git
synced 2025-05-10 22:18:03 +03:00
1890 lines
52 KiB
D
1890 lines
52 KiB
D
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/***************************
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* D programming language http://www.digitalmars.com/d/
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* Runtime support for byte array operations.
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* Based on code originally written by Burton Radons.
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* Placed in public domain.
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*/
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/* Contains SSE2 and MMX versions of certain operations for char, byte,
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* and ubyte ('a', 'g' and 'h' suffixes).
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*/
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import std.cpuid;
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version (Unittest)
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{
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/* This is so unit tests will test every CPU variant
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*/
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int cpuid;
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const int CPUID_MAX = 4;
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bool mmx() { return cpuid == 1 && std.cpuid.mmx(); }
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bool sse() { return cpuid == 2 && std.cpuid.sse(); }
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bool sse2() { return cpuid == 3 && std.cpuid.sse2(); }
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bool amd3dnow() { return cpuid == 4 && std.cpuid.amd3dnow(); }
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}
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else
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{
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alias std.cpuid.mmx mmx;
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alias std.cpuid.sse sse;
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alias std.cpuid.sse2 sse2;
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alias std.cpuid.amd3dnow amd3dnow;
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}
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//version = log;
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bool disjoint(T)(T[] a, T[] b)
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{
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return (a.ptr + a.length <= b.ptr || b.ptr + b.length <= a.ptr);
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}
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alias byte T;
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extern (C):
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/* ======================================================================== */
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/***********************
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* Computes:
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* a[] = b[] + value
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*/
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T[] _arraySliceExpAddSliceAssign_a(T[] a, T value, T[] b)
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{
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return _arraySliceExpAddSliceAssign_g(a, value, b);
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}
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T[] _arraySliceExpAddSliceAssign_h(T[] a, T value, T[] b)
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{
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return _arraySliceExpAddSliceAssign_g(a, value, b);
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}
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T[] _arraySliceExpAddSliceAssign_g(T[] a, T value, T[] b)
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in
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{
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assert(a.length == b.length);
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assert(disjoint(a, b));
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}
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body
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{
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//printf("_arraySliceExpAddSliceAssign_g()\n");
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auto aptr = a.ptr;
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auto aend = aptr + a.length;
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auto bptr = b.ptr;
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version (D_InlineAsm_X86)
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{
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// SSE2 aligned version is 1088% faster
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if (sse2() && a.length >= 64)
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{
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auto n = aptr + (a.length & ~63);
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uint l = cast(ubyte) value;
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l |= (l << 8);
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l |= (l << 16);
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if (((cast(uint) aptr | cast(uint) bptr) & 15) != 0)
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{
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asm // unaligned case
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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movd XMM4, l;
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pshufd XMM4, XMM4, 0;
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align 8;
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startaddsse2u:
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add ESI, 64;
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movdqu XMM0, [EAX];
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movdqu XMM1, [EAX+16];
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movdqu XMM2, [EAX+32];
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movdqu XMM3, [EAX+48];
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add EAX, 64;
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paddb XMM0, XMM4;
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paddb XMM1, XMM4;
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paddb XMM2, XMM4;
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paddb XMM3, XMM4;
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movdqu [ESI -64], XMM0;
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movdqu [ESI+16-64], XMM1;
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movdqu [ESI+32-64], XMM2;
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movdqu [ESI+48-64], XMM3;
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cmp ESI, EDI;
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jb startaddsse2u;
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mov aptr, ESI;
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mov bptr, EAX;
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}
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}
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else
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{
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asm // aligned case
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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movd XMM4, l;
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pshufd XMM4, XMM4, 0;
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align 8;
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startaddsse2a:
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add ESI, 64;
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movdqa XMM0, [EAX];
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movdqa XMM1, [EAX+16];
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movdqa XMM2, [EAX+32];
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movdqa XMM3, [EAX+48];
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add EAX, 64;
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paddb XMM0, XMM4;
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paddb XMM1, XMM4;
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paddb XMM2, XMM4;
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paddb XMM3, XMM4;
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movdqa [ESI -64], XMM0;
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movdqa [ESI+16-64], XMM1;
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movdqa [ESI+32-64], XMM2;
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movdqa [ESI+48-64], XMM3;
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cmp ESI, EDI;
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jb startaddsse2a;
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mov aptr, ESI;
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mov bptr, EAX;
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}
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}
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}
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else
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// MMX version is 1000% faster
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if (mmx() && a.length >= 32)
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{
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auto n = aptr + (a.length & ~31);
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uint l = cast(ubyte) value;
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l |= (l << 8);
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asm
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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movd MM4, l;
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pshufw MM4, MM4, 0;
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align 4;
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startaddmmx:
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add ESI, 32;
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movq MM0, [EAX];
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movq MM1, [EAX+8];
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movq MM2, [EAX+16];
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movq MM3, [EAX+24];
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add EAX, 32;
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paddb MM0, MM4;
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paddb MM1, MM4;
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paddb MM2, MM4;
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paddb MM3, MM4;
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movq [ESI -32], MM0;
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movq [ESI+8 -32], MM1;
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movq [ESI+16-32], MM2;
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movq [ESI+24-32], MM3;
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cmp ESI, EDI;
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jb startaddmmx;
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emms;
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mov aptr, ESI;
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mov bptr, EAX;
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}
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}
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/* trying to be fair and treat normal 32-bit cpu the same way as we do
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* the SIMD units, with unrolled asm. There's not enough registers,
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* really.
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*/
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else
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if (a.length >= 4)
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{
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auto n = aptr + (a.length & ~3);
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asm
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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mov CL, value;
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align 4;
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startadd386:
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add ESI, 4;
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mov DX, [EAX];
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mov BX, [EAX+2];
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add EAX, 4;
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add BL, CL;
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add BH, CL;
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add DL, CL;
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add DH, CL;
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mov [ESI -4], DX;
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mov [ESI+2 -4], BX;
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cmp ESI, EDI;
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jb startadd386;
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mov aptr, ESI;
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mov bptr, EAX;
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}
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}
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}
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while (aptr < aend)
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*aptr++ = cast(T)(*bptr++ + value);
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return a;
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}
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unittest
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{
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printf("_arraySliceExpAddSliceAssign_g unittest\n");
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for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
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{
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version (log) printf(" cpuid %d\n", cpuid);
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for (int j = 0; j < 2; j++)
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{
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const int dim = 67;
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T[] a = new T[dim + j]; // aligned on 16 byte boundary
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a = a[j .. dim + j]; // misalign for second iteration
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T[] b = new T[dim + j];
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b = b[j .. dim + j];
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T[] c = new T[dim + j];
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c = c[j .. dim + j];
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for (int i = 0; i < dim; i++)
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{ a[i] = cast(T)i;
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b[i] = cast(T)(i + 7);
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c[i] = cast(T)(i * 2);
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}
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c[] = a[] + 6;
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for (int i = 0; i < dim; i++)
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{
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if (c[i] != cast(T)(a[i] + 6))
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{
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printf("[%d]: %d != %d + 6\n", i, c[i], a[i]);
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assert(0);
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}
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}
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}
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}
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}
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/* ======================================================================== */
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/***********************
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* Computes:
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* a[] = b[] + c[]
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*/
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T[] _arraySliceSliceAddSliceAssign_a(T[] a, T[] c, T[] b)
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{
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return _arraySliceSliceAddSliceAssign_g(a, c, b);
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}
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T[] _arraySliceSliceAddSliceAssign_h(T[] a, T[] c, T[] b)
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{
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return _arraySliceSliceAddSliceAssign_g(a, c, b);
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}
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T[] _arraySliceSliceAddSliceAssign_g(T[] a, T[] c, T[] b)
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in
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{
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assert(a.length == b.length && b.length == c.length);
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assert(disjoint(a, b));
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assert(disjoint(a, c));
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assert(disjoint(b, c));
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}
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body
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{
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//printf("_arraySliceSliceAddSliceAssign_g()\n");
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auto aptr = a.ptr;
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auto aend = aptr + a.length;
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auto bptr = b.ptr;
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auto cptr = c.ptr;
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version (D_InlineAsm_X86)
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{
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// SSE2 aligned version is 5739% faster
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if (sse2() && a.length >= 64)
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{
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auto n = aptr + (a.length & ~63);
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if (((cast(uint) aptr | cast(uint) bptr | cast(uint) cptr) & 15) != 0)
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{
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version (log) printf("\tsse2 unaligned\n");
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asm // unaligned case
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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mov ECX, cptr;
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align 8;
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startaddlsse2u:
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add ESI, 64;
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movdqu XMM0, [EAX];
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movdqu XMM1, [EAX+16];
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movdqu XMM2, [EAX+32];
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movdqu XMM3, [EAX+48];
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add EAX, 64;
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movdqu XMM4, [ECX];
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movdqu XMM5, [ECX+16];
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movdqu XMM6, [ECX+32];
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movdqu XMM7, [ECX+48];
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add ECX, 64;
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paddb XMM0, XMM4;
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paddb XMM1, XMM5;
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paddb XMM2, XMM6;
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paddb XMM3, XMM7;
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movdqu [ESI -64], XMM0;
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movdqu [ESI+16-64], XMM1;
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movdqu [ESI+32-64], XMM2;
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movdqu [ESI+48-64], XMM3;
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cmp ESI, EDI;
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jb startaddlsse2u;
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mov aptr, ESI;
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mov bptr, EAX;
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mov cptr, ECX;
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}
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}
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else
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{
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version (log) printf("\tsse2 aligned\n");
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asm // aligned case
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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mov ECX, cptr;
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align 8;
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startaddlsse2a:
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add ESI, 64;
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movdqa XMM0, [EAX];
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movdqa XMM1, [EAX+16];
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movdqa XMM2, [EAX+32];
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movdqa XMM3, [EAX+48];
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add EAX, 64;
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movdqa XMM4, [ECX];
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movdqa XMM5, [ECX+16];
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movdqa XMM6, [ECX+32];
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movdqa XMM7, [ECX+48];
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add ECX, 64;
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paddb XMM0, XMM4;
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paddb XMM1, XMM5;
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paddb XMM2, XMM6;
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paddb XMM3, XMM7;
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movdqa [ESI -64], XMM0;
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movdqa [ESI+16-64], XMM1;
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movdqa [ESI+32-64], XMM2;
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movdqa [ESI+48-64], XMM3;
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cmp ESI, EDI;
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jb startaddlsse2a;
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mov aptr, ESI;
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mov bptr, EAX;
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mov cptr, ECX;
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}
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}
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}
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else
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// MMX version is 4428% faster
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if (mmx() && a.length >= 32)
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{
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version (log) printf("\tmmx\n");
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auto n = aptr + (a.length & ~31);
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asm
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{
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mov ESI, aptr;
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mov EDI, n;
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mov EAX, bptr;
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mov ECX, cptr;
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align 4;
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startaddlmmx:
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add ESI, 32;
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movq MM0, [EAX];
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movq MM1, [EAX+8];
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movq MM2, [EAX+16];
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movq MM3, [EAX+24];
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add EAX, 32;
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movq MM4, [ECX];
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movq MM5, [ECX+8];
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movq MM6, [ECX+16];
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movq MM7, [ECX+24];
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add ECX, 32;
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paddb MM0, MM4;
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paddb MM1, MM5;
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paddb MM2, MM6;
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paddb MM3, MM7;
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movq [ESI -32], MM0;
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movq [ESI+8 -32], MM1;
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movq [ESI+16-32], MM2;
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movq [ESI+24-32], MM3;
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cmp ESI, EDI;
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jb startaddlmmx;
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emms;
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mov aptr, ESI;
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mov bptr, EAX;
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mov cptr, ECX;
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}
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}
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}
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version (log) if (aptr < aend) printf("\tbase\n");
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while (aptr < aend)
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*aptr++ = cast(T)(*bptr++ + *cptr++);
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return a;
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}
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unittest
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{
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printf("_arraySliceSliceAddSliceAssign_g unittest\n");
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for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
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{
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version (log) printf(" cpuid %d\n", cpuid);
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for (int j = 0; j < 2; j++)
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{
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const int dim = 67;
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T[] a = new T[dim + j]; // aligned on 16 byte boundary
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a = a[j .. dim + j]; // misalign for second iteration
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T[] b = new T[dim + j];
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b = b[j .. dim + j];
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T[] c = new T[dim + j];
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c = c[j .. dim + j];
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for (int i = 0; i < dim; i++)
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{ a[i] = cast(T)i;
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b[i] = cast(T)(i + 7);
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c[i] = cast(T)(i * 2);
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}
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c[] = a[] + b[];
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for (int i = 0; i < dim; i++)
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{
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if (c[i] != cast(T)(a[i] + b[i]))
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{
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printf("[%d]: %d != %d + %d\n", i, c[i], a[i], b[i]);
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assert(0);
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}
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}
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}
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}
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}
|
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|
|
|
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/* ======================================================================== */
|
|
|
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/***********************
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* Computes:
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* a[] += value
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*/
|
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|
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T[] _arrayExpSliceAddass_a(T[] a, T value)
|
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{
|
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return _arrayExpSliceAddass_g(a, value);
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}
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|
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T[] _arrayExpSliceAddass_h(T[] a, T value)
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{
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return _arrayExpSliceAddass_g(a, value);
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}
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T[] _arrayExpSliceAddass_g(T[] a, T value)
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{
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//printf("_arrayExpSliceAddass_g(a.length = %d, value = %Lg)\n", a.length, cast(real)value);
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auto aptr = a.ptr;
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auto aend = aptr + a.length;
|
|
|
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version (D_InlineAsm_X86)
|
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{
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// SSE2 aligned version is 1578% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
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uint l = cast(ubyte) value;
|
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l |= (l << 8);
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l |= (l << 16);
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|
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if (((cast(uint) aptr) & 15) != 0)
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{
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asm // unaligned case
|
|
{
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mov ESI, aptr;
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mov EDI, n;
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movd XMM4, l;
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pshufd XMM4, XMM4, 0;
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|
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align 8;
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startaddasssse2u:
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movdqu XMM0, [ESI];
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movdqu XMM1, [ESI+16];
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movdqu XMM2, [ESI+32];
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movdqu XMM3, [ESI+48];
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add ESI, 64;
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paddb XMM0, XMM4;
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paddb XMM1, XMM4;
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paddb XMM2, XMM4;
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paddb XMM3, XMM4;
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movdqu [ESI -64], XMM0;
|
|
movdqu [ESI+16-64], XMM1;
|
|
movdqu [ESI+32-64], XMM2;
|
|
movdqu [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startaddasssse2u;
|
|
|
|
mov aptr, ESI;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startaddasssse2a:
|
|
movdqa XMM0, [ESI];
|
|
movdqa XMM1, [ESI+16];
|
|
movdqa XMM2, [ESI+32];
|
|
movdqa XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
paddb XMM0, XMM4;
|
|
paddb XMM1, XMM4;
|
|
paddb XMM2, XMM4;
|
|
paddb XMM3, XMM4;
|
|
movdqa [ESI -64], XMM0;
|
|
movdqa [ESI+16-64], XMM1;
|
|
movdqa [ESI+32-64], XMM2;
|
|
movdqa [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startaddasssse2a;
|
|
|
|
mov aptr, ESI;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 1721% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
movd MM4, l;
|
|
pshufw MM4, MM4, 0;
|
|
|
|
align 8;
|
|
startaddassmmx:
|
|
movq MM0, [ESI];
|
|
movq MM1, [ESI+8];
|
|
movq MM2, [ESI+16];
|
|
movq MM3, [ESI+24];
|
|
add ESI, 32;
|
|
paddb MM0, MM4;
|
|
paddb MM1, MM4;
|
|
paddb MM2, MM4;
|
|
paddb MM3, MM4;
|
|
movq [ESI -32], MM0;
|
|
movq [ESI+8 -32], MM1;
|
|
movq [ESI+16-32], MM2;
|
|
movq [ESI+24-32], MM3;
|
|
cmp ESI, EDI;
|
|
jb startaddassmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
}
|
|
}
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ += value;
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arrayExpSliceAddass_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
a[] = c[];
|
|
c[] += 6;
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(a[i] + 6))
|
|
{
|
|
printf("[%d]: %d != %d + 6\n", i, c[i], a[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/***********************
|
|
* Computes:
|
|
* a[] += b[]
|
|
*/
|
|
|
|
T[] _arraySliceSliceAddass_a(T[] a, T[] b)
|
|
{
|
|
return _arraySliceSliceAddass_g(a, b);
|
|
}
|
|
|
|
T[] _arraySliceSliceAddass_h(T[] a, T[] b)
|
|
{
|
|
return _arraySliceSliceAddass_g(a, b);
|
|
}
|
|
|
|
T[] _arraySliceSliceAddass_g(T[] a, T[] b)
|
|
in
|
|
{
|
|
assert (a.length == b.length);
|
|
assert (disjoint(a, b));
|
|
}
|
|
body
|
|
{
|
|
//printf("_arraySliceSliceAddass_g()\n");
|
|
auto aptr = a.ptr;
|
|
auto aend = aptr + a.length;
|
|
auto bptr = b.ptr;
|
|
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
// SSE2 aligned version is 4727% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
|
if (((cast(uint) aptr | cast(uint) bptr) & 15) != 0)
|
|
{
|
|
asm // unaligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov ECX, bptr;
|
|
|
|
align 8;
|
|
startaddasslsse2u:
|
|
movdqu XMM0, [ESI];
|
|
movdqu XMM1, [ESI+16];
|
|
movdqu XMM2, [ESI+32];
|
|
movdqu XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
movdqu XMM4, [ECX];
|
|
movdqu XMM5, [ECX+16];
|
|
movdqu XMM6, [ECX+32];
|
|
movdqu XMM7, [ECX+48];
|
|
add ECX, 64;
|
|
paddb XMM0, XMM4;
|
|
paddb XMM1, XMM5;
|
|
paddb XMM2, XMM6;
|
|
paddb XMM3, XMM7;
|
|
movdqu [ESI -64], XMM0;
|
|
movdqu [ESI+16-64], XMM1;
|
|
movdqu [ESI+32-64], XMM2;
|
|
movdqu [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startaddasslsse2u;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, ECX;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov ECX, bptr;
|
|
|
|
align 8;
|
|
startaddasslsse2a:
|
|
movdqa XMM0, [ESI];
|
|
movdqa XMM1, [ESI+16];
|
|
movdqa XMM2, [ESI+32];
|
|
movdqa XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
movdqa XMM4, [ECX];
|
|
movdqa XMM5, [ECX+16];
|
|
movdqa XMM6, [ECX+32];
|
|
movdqa XMM7, [ECX+48];
|
|
add ECX, 64;
|
|
paddb XMM0, XMM4;
|
|
paddb XMM1, XMM5;
|
|
paddb XMM2, XMM6;
|
|
paddb XMM3, XMM7;
|
|
movdqa [ESI -64], XMM0;
|
|
movdqa [ESI+16-64], XMM1;
|
|
movdqa [ESI+32-64], XMM2;
|
|
movdqa [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startaddasslsse2a;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, ECX;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 3059% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov ECX, bptr;
|
|
|
|
align 8;
|
|
startaddasslmmx:
|
|
movq MM0, [ESI];
|
|
movq MM1, [ESI+8];
|
|
movq MM2, [ESI+16];
|
|
movq MM3, [ESI+24];
|
|
add ESI, 32;
|
|
movq MM4, [ECX];
|
|
movq MM5, [ECX+8];
|
|
movq MM6, [ECX+16];
|
|
movq MM7, [ECX+24];
|
|
add ECX, 32;
|
|
paddb MM0, MM4;
|
|
paddb MM1, MM5;
|
|
paddb MM2, MM6;
|
|
paddb MM3, MM7;
|
|
movq [ESI -32], MM0;
|
|
movq [ESI+8 -32], MM1;
|
|
movq [ESI+16-32], MM2;
|
|
movq [ESI+24-32], MM3;
|
|
cmp ESI, EDI;
|
|
jb startaddasslmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
mov bptr, ECX;
|
|
}
|
|
}
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ += *bptr++;
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arraySliceSliceAddass_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
a[] = c[];
|
|
c[] += b[];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(a[i] + b[i]))
|
|
{
|
|
printf("[%d]: %d != %d + %d\n", i, c[i], a[i], b[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
|
|
/***********************
|
|
* Computes:
|
|
* a[] = b[] - value
|
|
*/
|
|
|
|
T[] _arraySliceExpMinSliceAssign_a(T[] a, T value, T[] b)
|
|
{
|
|
return _arraySliceExpMinSliceAssign_g(a, value, b);
|
|
}
|
|
|
|
T[] _arraySliceExpMinSliceAssign_h(T[] a, T value, T[] b)
|
|
{
|
|
return _arraySliceExpMinSliceAssign_g(a, value, b);
|
|
}
|
|
|
|
T[] _arraySliceExpMinSliceAssign_g(T[] a, T value, T[] b)
|
|
in
|
|
{
|
|
assert(a.length == b.length);
|
|
assert(disjoint(a, b));
|
|
}
|
|
body
|
|
{
|
|
//printf("_arraySliceExpMinSliceAssign_g()\n");
|
|
auto aptr = a.ptr;
|
|
auto aend = aptr + a.length;
|
|
auto bptr = b.ptr;
|
|
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
// SSE2 aligned version is 1189% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
l |= (l << 16);
|
|
|
|
if (((cast(uint) aptr | cast(uint) bptr) & 15) != 0)
|
|
{
|
|
asm // unaligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startsubsse2u:
|
|
add ESI, 64;
|
|
movdqu XMM0, [EAX];
|
|
movdqu XMM1, [EAX+16];
|
|
movdqu XMM2, [EAX+32];
|
|
movdqu XMM3, [EAX+48];
|
|
add EAX, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM4;
|
|
psubb XMM2, XMM4;
|
|
psubb XMM3, XMM4;
|
|
movdqu [ESI -64], XMM0;
|
|
movdqu [ESI+16-64], XMM1;
|
|
movdqu [ESI+32-64], XMM2;
|
|
movdqu [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsubsse2u;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startsubsse2a:
|
|
add ESI, 64;
|
|
movdqa XMM0, [EAX];
|
|
movdqa XMM1, [EAX+16];
|
|
movdqa XMM2, [EAX+32];
|
|
movdqa XMM3, [EAX+48];
|
|
add EAX, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM4;
|
|
psubb XMM2, XMM4;
|
|
psubb XMM3, XMM4;
|
|
movdqa [ESI -64], XMM0;
|
|
movdqa [ESI+16-64], XMM1;
|
|
movdqa [ESI+32-64], XMM2;
|
|
movdqa [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsubsse2a;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 1079% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
movd MM4, l;
|
|
pshufw MM4, MM4, 0;
|
|
|
|
align 4;
|
|
startsubmmx:
|
|
add ESI, 32;
|
|
movq MM0, [EAX];
|
|
movq MM1, [EAX+8];
|
|
movq MM2, [EAX+16];
|
|
movq MM3, [EAX+24];
|
|
add EAX, 32;
|
|
psubb MM0, MM4;
|
|
psubb MM1, MM4;
|
|
psubb MM2, MM4;
|
|
psubb MM3, MM4;
|
|
movq [ESI -32], MM0;
|
|
movq [ESI+8 -32], MM1;
|
|
movq [ESI+16-32], MM2;
|
|
movq [ESI+24-32], MM3;
|
|
cmp ESI, EDI;
|
|
jb startsubmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
// trying to be fair and treat normal 32-bit cpu the same way as we do the SIMD units, with unrolled asm. There's not enough registers, really.
|
|
else
|
|
if (a.length >= 4)
|
|
{
|
|
auto n = aptr + (a.length & ~3);
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
mov CL, value;
|
|
|
|
align 4;
|
|
startsub386:
|
|
add ESI, 4;
|
|
mov DX, [EAX];
|
|
mov BX, [EAX+2];
|
|
add EAX, 4;
|
|
sub BL, CL;
|
|
sub BH, CL;
|
|
sub DL, CL;
|
|
sub DH, CL;
|
|
mov [ESI -4], DX;
|
|
mov [ESI+2 -4], BX;
|
|
cmp ESI, EDI;
|
|
jb startsub386;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ = cast(T)(*bptr++ - value);
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arraySliceExpMinSliceAssign_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
a[] = c[];
|
|
c[] = b[] - 6;
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(b[i] - 6))
|
|
{
|
|
printf("[%d]: %d != %d - 6\n", i, c[i], b[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/***********************
|
|
* Computes:
|
|
* a[] = value - b[]
|
|
*/
|
|
|
|
T[] _arrayExpSliceMinSliceAssign_a(T[] a, T[] b, T value)
|
|
{
|
|
return _arrayExpSliceMinSliceAssign_g(a, b, value);
|
|
}
|
|
|
|
T[] _arrayExpSliceMinSliceAssign_h(T[] a, T[] b, T value)
|
|
{
|
|
return _arrayExpSliceMinSliceAssign_g(a, b, value);
|
|
}
|
|
|
|
T[] _arrayExpSliceMinSliceAssign_g(T[] a, T[] b, T value)
|
|
in
|
|
{
|
|
assert(a.length == b.length);
|
|
assert(disjoint(a, b));
|
|
}
|
|
body
|
|
{
|
|
//printf("_arrayExpSliceMinSliceAssign_g()\n");
|
|
auto aptr = a.ptr;
|
|
auto aend = aptr + a.length;
|
|
auto bptr = b.ptr;
|
|
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
// SSE2 aligned version is 8748% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
l |= (l << 16);
|
|
|
|
if (((cast(uint) aptr | cast(uint) bptr) & 15) != 0)
|
|
{
|
|
asm // unaligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startsubrsse2u:
|
|
add ESI, 64;
|
|
movdqa XMM5, XMM4;
|
|
movdqa XMM6, XMM4;
|
|
movdqu XMM0, [EAX];
|
|
movdqu XMM1, [EAX+16];
|
|
psubb XMM5, XMM0;
|
|
psubb XMM6, XMM1;
|
|
movdqu [ESI -64], XMM5;
|
|
movdqu [ESI+16-64], XMM6;
|
|
movdqa XMM5, XMM4;
|
|
movdqa XMM6, XMM4;
|
|
movdqu XMM2, [EAX+32];
|
|
movdqu XMM3, [EAX+48];
|
|
add EAX, 64;
|
|
psubb XMM5, XMM2;
|
|
psubb XMM6, XMM3;
|
|
movdqu [ESI+32-64], XMM5;
|
|
movdqu [ESI+48-64], XMM6;
|
|
cmp ESI, EDI;
|
|
jb startsubrsse2u;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startsubrsse2a:
|
|
add ESI, 64;
|
|
movdqa XMM5, XMM4;
|
|
movdqa XMM6, XMM4;
|
|
movdqa XMM0, [EAX];
|
|
movdqa XMM1, [EAX+16];
|
|
psubb XMM5, XMM0;
|
|
psubb XMM6, XMM1;
|
|
movdqa [ESI -64], XMM5;
|
|
movdqa [ESI+16-64], XMM6;
|
|
movdqa XMM5, XMM4;
|
|
movdqa XMM6, XMM4;
|
|
movdqa XMM2, [EAX+32];
|
|
movdqa XMM3, [EAX+48];
|
|
add EAX, 64;
|
|
psubb XMM5, XMM2;
|
|
psubb XMM6, XMM3;
|
|
movdqa [ESI+32-64], XMM5;
|
|
movdqa [ESI+48-64], XMM6;
|
|
cmp ESI, EDI;
|
|
jb startsubrsse2a;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 7397% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
movd MM4, l;
|
|
pshufw MM4, MM4, 0;
|
|
|
|
align 4;
|
|
startsubrmmx:
|
|
add ESI, 32;
|
|
movq MM5, MM4;
|
|
movq MM6, MM4;
|
|
movq MM0, [EAX];
|
|
movq MM1, [EAX+8];
|
|
psubb MM5, MM0;
|
|
psubb MM6, MM1;
|
|
movq [ESI -32], MM5;
|
|
movq [ESI+8 -32], MM6;
|
|
movq MM5, MM4;
|
|
movq MM6, MM4;
|
|
movq MM2, [EAX+16];
|
|
movq MM3, [EAX+24];
|
|
add EAX, 32;
|
|
psubb MM5, MM2;
|
|
psubb MM6, MM3;
|
|
movq [ESI+16-32], MM5;
|
|
movq [ESI+24-32], MM6;
|
|
cmp ESI, EDI;
|
|
jb startsubrmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ = cast(T)(value - *bptr++);
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arrayExpSliceMinSliceAssign_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
a[] = c[];
|
|
c[] = 6 - b[];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(6 - b[i]))
|
|
{
|
|
printf("[%d]: %d != 6 - %d\n", i, c[i], b[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/***********************
|
|
* Computes:
|
|
* a[] = b[] - c[]
|
|
*/
|
|
|
|
T[] _arraySliceSliceMinSliceAssign_a(T[] a, T[] c, T[] b)
|
|
{
|
|
return _arraySliceSliceMinSliceAssign_g(a, c, b);
|
|
}
|
|
|
|
T[] _arraySliceSliceMinSliceAssign_h(T[] a, T[] c, T[] b)
|
|
{
|
|
return _arraySliceSliceMinSliceAssign_g(a, c, b);
|
|
}
|
|
|
|
T[] _arraySliceSliceMinSliceAssign_g(T[] a, T[] c, T[] b)
|
|
in
|
|
{
|
|
assert(a.length == b.length && b.length == c.length);
|
|
assert(disjoint(a, b));
|
|
assert(disjoint(a, c));
|
|
assert(disjoint(b, c));
|
|
}
|
|
body
|
|
{
|
|
auto aptr = a.ptr;
|
|
auto aend = aptr + a.length;
|
|
auto bptr = b.ptr;
|
|
auto cptr = c.ptr;
|
|
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
// SSE2 aligned version is 5756% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
|
if (((cast(uint) aptr | cast(uint) bptr | cast(uint) cptr) & 15) != 0)
|
|
{
|
|
asm // unaligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
mov ECX, cptr;
|
|
|
|
align 8;
|
|
startsublsse2u:
|
|
add ESI, 64;
|
|
movdqu XMM0, [EAX];
|
|
movdqu XMM1, [EAX+16];
|
|
movdqu XMM2, [EAX+32];
|
|
movdqu XMM3, [EAX+48];
|
|
add EAX, 64;
|
|
movdqu XMM4, [ECX];
|
|
movdqu XMM5, [ECX+16];
|
|
movdqu XMM6, [ECX+32];
|
|
movdqu XMM7, [ECX+48];
|
|
add ECX, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM5;
|
|
psubb XMM2, XMM6;
|
|
psubb XMM3, XMM7;
|
|
movdqu [ESI -64], XMM0;
|
|
movdqu [ESI+16-64], XMM1;
|
|
movdqu [ESI+32-64], XMM2;
|
|
movdqu [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsublsse2u;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
mov cptr, ECX;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
mov ECX, cptr;
|
|
|
|
align 8;
|
|
startsublsse2a:
|
|
add ESI, 64;
|
|
movdqa XMM0, [EAX];
|
|
movdqa XMM1, [EAX+16];
|
|
movdqa XMM2, [EAX+32];
|
|
movdqa XMM3, [EAX+48];
|
|
add EAX, 64;
|
|
movdqa XMM4, [ECX];
|
|
movdqa XMM5, [ECX+16];
|
|
movdqa XMM6, [ECX+32];
|
|
movdqa XMM7, [ECX+48];
|
|
add ECX, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM5;
|
|
psubb XMM2, XMM6;
|
|
psubb XMM3, XMM7;
|
|
movdqa [ESI -64], XMM0;
|
|
movdqa [ESI+16-64], XMM1;
|
|
movdqa [ESI+32-64], XMM2;
|
|
movdqa [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsublsse2a;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
mov cptr, ECX;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 4428% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov EAX, bptr;
|
|
mov ECX, cptr;
|
|
|
|
align 8;
|
|
startsublmmx:
|
|
add ESI, 32;
|
|
movq MM0, [EAX];
|
|
movq MM1, [EAX+8];
|
|
movq MM2, [EAX+16];
|
|
movq MM3, [EAX+24];
|
|
add EAX, 32;
|
|
movq MM4, [ECX];
|
|
movq MM5, [ECX+8];
|
|
movq MM6, [ECX+16];
|
|
movq MM7, [ECX+24];
|
|
add ECX, 32;
|
|
psubb MM0, MM4;
|
|
psubb MM1, MM5;
|
|
psubb MM2, MM6;
|
|
psubb MM3, MM7;
|
|
movq [ESI -32], MM0;
|
|
movq [ESI+8 -32], MM1;
|
|
movq [ESI+16-32], MM2;
|
|
movq [ESI+24-32], MM3;
|
|
cmp ESI, EDI;
|
|
jb startsublmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
mov bptr, EAX;
|
|
mov cptr, ECX;
|
|
}
|
|
}
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ = cast(T)(*bptr++ - *cptr++);
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arraySliceSliceMinSliceAssign_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
c[] = a[] - b[];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(a[i] - b[i]))
|
|
{
|
|
printf("[%d]: %d != %d - %d\n", i, c[i], a[i], b[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/***********************
|
|
* Computes:
|
|
* a[] -= value
|
|
*/
|
|
|
|
T[] _arrayExpSliceMinass_a(T[] a, T value)
|
|
{
|
|
return _arrayExpSliceMinass_g(a, value);
|
|
}
|
|
|
|
T[] _arrayExpSliceMinass_h(T[] a, T value)
|
|
{
|
|
return _arrayExpSliceMinass_g(a, value);
|
|
}
|
|
|
|
T[] _arrayExpSliceMinass_g(T[] a, T value)
|
|
{
|
|
//printf("_arrayExpSliceMinass_g(a.length = %d, value = %Lg)\n", a.length, cast(real)value);
|
|
auto aptr = a.ptr;
|
|
auto aend = aptr + a.length;
|
|
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
// SSE2 aligned version is 1577% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
l |= (l << 16);
|
|
|
|
if (((cast(uint) aptr) & 15) != 0)
|
|
{
|
|
asm // unaligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startsubasssse2u:
|
|
movdqu XMM0, [ESI];
|
|
movdqu XMM1, [ESI+16];
|
|
movdqu XMM2, [ESI+32];
|
|
movdqu XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM4;
|
|
psubb XMM2, XMM4;
|
|
psubb XMM3, XMM4;
|
|
movdqu [ESI -64], XMM0;
|
|
movdqu [ESI+16-64], XMM1;
|
|
movdqu [ESI+32-64], XMM2;
|
|
movdqu [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsubasssse2u;
|
|
|
|
mov aptr, ESI;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
movd XMM4, l;
|
|
pshufd XMM4, XMM4, 0;
|
|
|
|
align 8;
|
|
startsubasssse2a:
|
|
movdqa XMM0, [ESI];
|
|
movdqa XMM1, [ESI+16];
|
|
movdqa XMM2, [ESI+32];
|
|
movdqa XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM4;
|
|
psubb XMM2, XMM4;
|
|
psubb XMM3, XMM4;
|
|
movdqa [ESI -64], XMM0;
|
|
movdqa [ESI+16-64], XMM1;
|
|
movdqa [ESI+32-64], XMM2;
|
|
movdqa [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsubasssse2a;
|
|
|
|
mov aptr, ESI;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 1577% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
uint l = cast(ubyte) value;
|
|
l |= (l << 8);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
movd MM4, l;
|
|
pshufw MM4, MM4, 0;
|
|
|
|
align 8;
|
|
startsubassmmx:
|
|
movq MM0, [ESI];
|
|
movq MM1, [ESI+8];
|
|
movq MM2, [ESI+16];
|
|
movq MM3, [ESI+24];
|
|
add ESI, 32;
|
|
psubb MM0, MM4;
|
|
psubb MM1, MM4;
|
|
psubb MM2, MM4;
|
|
psubb MM3, MM4;
|
|
movq [ESI -32], MM0;
|
|
movq [ESI+8 -32], MM1;
|
|
movq [ESI+16-32], MM2;
|
|
movq [ESI+24-32], MM3;
|
|
cmp ESI, EDI;
|
|
jb startsubassmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
}
|
|
}
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ -= value;
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arrayExpSliceMinass_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
a[] = c[];
|
|
c[] -= 6;
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(a[i] - 6))
|
|
{
|
|
printf("[%d]: %d != %d - 6\n", i, c[i], a[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/***********************
|
|
* Computes:
|
|
* a[] -= b[]
|
|
*/
|
|
|
|
T[] _arraySliceSliceMinass_a(T[] a, T[] b)
|
|
{
|
|
return _arraySliceSliceMinass_g(a, b);
|
|
}
|
|
|
|
T[] _arraySliceSliceMinass_h(T[] a, T[] b)
|
|
{
|
|
return _arraySliceSliceMinass_g(a, b);
|
|
}
|
|
|
|
T[] _arraySliceSliceMinass_g(T[] a, T[] b)
|
|
in
|
|
{
|
|
assert (a.length == b.length);
|
|
assert (disjoint(a, b));
|
|
}
|
|
body
|
|
{
|
|
//printf("_arraySliceSliceMinass_g()\n");
|
|
auto aptr = a.ptr;
|
|
auto aend = aptr + a.length;
|
|
auto bptr = b.ptr;
|
|
|
|
version (D_InlineAsm_X86)
|
|
{
|
|
// SSE2 aligned version is 4800% faster
|
|
if (sse2() && a.length >= 64)
|
|
{
|
|
auto n = aptr + (a.length & ~63);
|
|
|
|
if (((cast(uint) aptr | cast(uint) bptr) & 15) != 0)
|
|
{
|
|
asm // unaligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov ECX, bptr;
|
|
|
|
align 8;
|
|
startsubasslsse2u:
|
|
movdqu XMM0, [ESI];
|
|
movdqu XMM1, [ESI+16];
|
|
movdqu XMM2, [ESI+32];
|
|
movdqu XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
movdqu XMM4, [ECX];
|
|
movdqu XMM5, [ECX+16];
|
|
movdqu XMM6, [ECX+32];
|
|
movdqu XMM7, [ECX+48];
|
|
add ECX, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM5;
|
|
psubb XMM2, XMM6;
|
|
psubb XMM3, XMM7;
|
|
movdqu [ESI -64], XMM0;
|
|
movdqu [ESI+16-64], XMM1;
|
|
movdqu [ESI+32-64], XMM2;
|
|
movdqu [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsubasslsse2u;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, ECX;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
asm // aligned case
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov ECX, bptr;
|
|
|
|
align 8;
|
|
startsubasslsse2a:
|
|
movdqa XMM0, [ESI];
|
|
movdqa XMM1, [ESI+16];
|
|
movdqa XMM2, [ESI+32];
|
|
movdqa XMM3, [ESI+48];
|
|
add ESI, 64;
|
|
movdqa XMM4, [ECX];
|
|
movdqa XMM5, [ECX+16];
|
|
movdqa XMM6, [ECX+32];
|
|
movdqa XMM7, [ECX+48];
|
|
add ECX, 64;
|
|
psubb XMM0, XMM4;
|
|
psubb XMM1, XMM5;
|
|
psubb XMM2, XMM6;
|
|
psubb XMM3, XMM7;
|
|
movdqa [ESI -64], XMM0;
|
|
movdqa [ESI+16-64], XMM1;
|
|
movdqa [ESI+32-64], XMM2;
|
|
movdqa [ESI+48-64], XMM3;
|
|
cmp ESI, EDI;
|
|
jb startsubasslsse2a;
|
|
|
|
mov aptr, ESI;
|
|
mov bptr, ECX;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
// MMX version is 3107% faster
|
|
if (mmx() && a.length >= 32)
|
|
{
|
|
|
|
auto n = aptr + (a.length & ~31);
|
|
|
|
asm
|
|
{
|
|
mov ESI, aptr;
|
|
mov EDI, n;
|
|
mov ECX, bptr;
|
|
|
|
align 8;
|
|
startsubasslmmx:
|
|
movq MM0, [ESI];
|
|
movq MM1, [ESI+8];
|
|
movq MM2, [ESI+16];
|
|
movq MM3, [ESI+24];
|
|
add ESI, 32;
|
|
movq MM4, [ECX];
|
|
movq MM5, [ECX+8];
|
|
movq MM6, [ECX+16];
|
|
movq MM7, [ECX+24];
|
|
add ECX, 32;
|
|
psubb MM0, MM4;
|
|
psubb MM1, MM5;
|
|
psubb MM2, MM6;
|
|
psubb MM3, MM7;
|
|
movq [ESI -32], MM0;
|
|
movq [ESI+8 -32], MM1;
|
|
movq [ESI+16-32], MM2;
|
|
movq [ESI+24-32], MM3;
|
|
cmp ESI, EDI;
|
|
jb startsubasslmmx;
|
|
|
|
emms;
|
|
mov aptr, ESI;
|
|
mov bptr, ECX;
|
|
}
|
|
}
|
|
}
|
|
|
|
while (aptr < aend)
|
|
*aptr++ -= *bptr++;
|
|
|
|
return a;
|
|
}
|
|
|
|
unittest
|
|
{
|
|
printf("_arraySliceSliceMinass_g unittest\n");
|
|
|
|
for (cpuid = 0; cpuid < CPUID_MAX; cpuid++)
|
|
{
|
|
version (log) printf(" cpuid %d\n", cpuid);
|
|
|
|
for (int j = 0; j < 2; j++)
|
|
{
|
|
const int dim = 67;
|
|
T[] a = new T[dim + j]; // aligned on 16 byte boundary
|
|
a = a[j .. dim + j]; // misalign for second iteration
|
|
T[] b = new T[dim + j];
|
|
b = b[j .. dim + j];
|
|
T[] c = new T[dim + j];
|
|
c = c[j .. dim + j];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{ a[i] = cast(T)i;
|
|
b[i] = cast(T)(i + 7);
|
|
c[i] = cast(T)(i * 2);
|
|
}
|
|
|
|
a[] = c[];
|
|
c[] -= b[];
|
|
|
|
for (int i = 0; i < dim; i++)
|
|
{
|
|
if (c[i] != cast(T)(a[i] - b[i]))
|
|
{
|
|
printf("[%d]: %d != %d - %d\n", i, c[i], a[i], b[i]);
|
|
assert(0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|