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ae9d43c167
I.e., llvm/CodeGen/CommandFlags.h which in turn includes llvm/MC/MCTargetOptionsCommandFlags.h. This gets rid of a few duplicates on our side and includes about 35 (depending on LLVM version) new command-line options. LLVM provides a helper function to set up the TargetOptions according to (most of) these options. Newer LLVM versions may add new options and we'll automatically inherit them, including setting up the TargetOptions accordingly. I did my best (TM) to remove a few unused/undesirable options and hide all remaining new ones except for `-fp-contract`. The lists will need to be tweaked from time to time.
83 lines
2.9 KiB
C++
83 lines
2.9 KiB
C++
//===-- gen/dcompute/targetCUDA.cpp ---------------------------------------===//
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//
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// LDC – the LLVM D compiler
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//
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// This file is distributed under the BSD-style LDC license. See the LICENSE
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// file for details.
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//
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//===----------------------------------------------------------------------===//
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#if LDC_LLVM_SUPPORTED_TARGET_NVPTX
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#include "gen/dcompute/target.h"
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#include "gen/dcompute/druntime.h"
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#include "gen/metadata.h"
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#include "gen/abi-nvptx.h"
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#include "gen/logger.h"
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#include "gen/optimizer.h"
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#include "gen/to_string.h"
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#include "llvm/Transforms/Scalar.h"
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#include "driver/targetmachine.h"
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#include <cstring>
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namespace {
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class TargetCUDA : public DComputeTarget {
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public:
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TargetCUDA(llvm::LLVMContext &c, int sm)
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: DComputeTarget(
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c, sm, CUDA, "cuda", "ptx", createNVPTXABI(),
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// Map from nominal DCompute address space to NVPTX address space.
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// see $LLVM_ROOT/docs/docs/NVPTXUsage.rst section Address Spaces
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{{5, 1, 3, 4, 0}}) {
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std::string dl =
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global.params.is64bit
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? "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:"
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"32-"
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"f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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: "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:"
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"32-"
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"f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64";
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_ir = new IRState("dcomputeTargetCUDA", ctx);
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_ir->module.setTargetTriple(global.params.is64bit ? "nvptx64-nvidia-cuda"
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: "nvptx-nvidia-cuda");
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_ir->module.setDataLayout(dl);
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_ir->dcomputetarget = this;
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}
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void addMetadata() override {
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// sm version?
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}
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void setGTargetMachine() override {
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const bool is64 = global.params.is64bit;
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gTargetMachine = createTargetMachine(
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is64 ? "nvptx64-nvidia-cuda" : "nvptx-nvidia-cuda",
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is64 ? "nvptx64" : "nvptx", "sm_" + ldc::to_string(tversion / 10), {},
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is64 ? ExplicitBitness::M64 : ExplicitBitness::M32, ::FloatABI::Hard,
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llvm::Reloc::Static, llvm::CodeModel::Medium, codeGenOptLevel(),
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false);
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}
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void addKernelMetadata(FuncDeclaration *df, llvm::Function *llf) override {
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// TODO: Handle Function attibutes
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llvm::NamedMDNode *na =
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_ir->module.getOrInsertNamedMetadata("nvvm.annotations");
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llvm::Metadata *fn = llvm::ConstantAsMetadata::get(llf);
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llvm::Metadata *kstr = llvm::MDString::get(ctx, "kernel");
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llvm::Metadata *one = llvm::ConstantAsMetadata::get(
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llvm::ConstantInt::get(llvm::IntegerType::get(ctx, 32), 1));
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llvm::Metadata *arr[] = {fn, kstr, one};
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llvm::MDNode *tup = llvm::MDTuple::get(ctx, arr);
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na->addOperand(tup);
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}
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};
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} // anonymous namespace.
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DComputeTarget *createCUDATarget(llvm::LLVMContext &c, int sm) {
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return new TargetCUDA(c, sm);
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};
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#endif // LDC_LLVM_SUPPORTED_TARGET_NVPTX
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