mirror of
https://github.com/ldc-developers/ldc.git
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d949688216
Modern Linux distributions have their toolchain generate PIC code for additional security features (like ASLR). Since there is no (sane) way to detect whether the toolchain defaults to PIC code, we simply default to PIC code on all Linux distributions to avoid linking issues on these OSes. The relocation model can be switched back to non-PIC code manually at any time.
608 lines
19 KiB
C++
608 lines
19 KiB
C++
//===-- targetmachine.cpp -------------------------------------------------===//
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//
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// LDC – the LLVM D compiler
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//
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// This file is distributed under the BSD-style LDC license. See the LICENSE
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// file for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Note: The target CPU detection logic has been adapted from Clang
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// (Tools.cpp and ToolChain.cpp in lib/Driver, the latter seems to have the
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// more up-to-date version).
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//
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//===----------------------------------------------------------------------===//
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#include "driver/targetmachine.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "mars.h"
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#include "gen/logger.h"
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#if LDC_LLVM_VER >= 307
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#include "driver/cl_options.h"
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static const char *getABI(const llvm::Triple &triple) {
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llvm::StringRef ABIName(opts::mABI);
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if (ABIName != "") {
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switch (triple.getArch()) {
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case llvm::Triple::arm:
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case llvm::Triple::armeb:
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if (ABIName.startswith("aapcs"))
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return "aapcs";
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if (ABIName.startswith("eabi"))
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return "apcs";
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break;
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case llvm::Triple::mips:
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case llvm::Triple::mipsel:
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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if (ABIName.startswith("o32"))
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return "o32";
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if (ABIName.startswith("n32"))
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return "n32";
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if (ABIName.startswith("n64"))
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return "n64";
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if (ABIName.startswith("eabi"))
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return "eabi";
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break;
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case llvm::Triple::ppc64:
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case llvm::Triple::ppc64le:
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if (ABIName.startswith("elfv1"))
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return "elfv1";
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if (ABIName.startswith("elfv2"))
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return "elfv2";
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break;
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default:
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break;
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}
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warning(Loc(), "Unknown ABI %s - using default ABI instead",
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ABIName.str().c_str());
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}
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switch (triple.getArch()) {
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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return "n32";
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case llvm::Triple::ppc64:
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return "elfv1";
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case llvm::Triple::ppc64le:
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return "elfv2";
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default:
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return "";
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}
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}
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#endif
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extern llvm::TargetMachine *gTargetMachine;
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MipsABI::Type getMipsABI() {
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#if LDC_LLVM_VER >= 307
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// eabi can only be set on the commandline
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if (strncmp(opts::mABI.c_str(), "eabi", 4) == 0)
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return MipsABI::EABI;
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else {
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#if LDC_LLVM_VER >= 308
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const llvm::DataLayout dl = gTargetMachine->createDataLayout();
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#else
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const llvm::DataLayout &dl = *gTargetMachine->getDataLayout();
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#endif
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if (dl.getPointerSizeInBits() == 64)
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return MipsABI::N64;
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#if LDC_LLVM_VER >= 309
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else if (dl.getLargestLegalIntTypeSizeInBits() == 64)
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#else
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else if (dl.getLargestLegalIntTypeSize() == 64)
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#endif
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return MipsABI::N32;
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else
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return MipsABI::O32;
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}
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#else
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llvm::StringRef features = gTargetMachine->getTargetFeatureString();
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if (features.find("+o32") != std::string::npos) {
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return MipsABI::O32;
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}
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if (features.find("+n32") != std::string::npos) {
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return MipsABI::N32;
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}
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if (features.find("+n64") != std::string::npos) {
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return MipsABI::N32;
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}
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if (features.find("+eabi") != std::string::npos) {
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return MipsABI::EABI;
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}
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return MipsABI::Unknown;
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#endif
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}
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static std::string getX86TargetCPU(const llvm::Triple &triple) {
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// Select the default CPU if none was given (or detection failed).
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// Intel Macs are relatively recent, take advantage of that.
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if (triple.isOSDarwin()) {
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return triple.isArch64Bit() ? "core2" : "yonah";
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}
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// Everything else goes to x86-64 in 64-bit mode.
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if (triple.isArch64Bit()) {
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return "x86-64";
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}
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if (triple.getOSName().startswith("haiku")) {
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return "i586";
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}
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if (triple.getOSName().startswith("openbsd")) {
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return "i486";
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}
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if (triple.getOSName().startswith("bitrig")) {
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return "i686";
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}
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if (triple.getOSName().startswith("freebsd")) {
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return "i486";
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}
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if (triple.getOSName().startswith("netbsd")) {
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return "i486";
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}
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if (triple.getOSName().startswith("openbsd")) {
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return "i486";
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}
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if (triple.getOSName().startswith("dragonfly")) {
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return "i486";
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}
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// All x86 devices running Android have core2 as their common
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// denominator. This makes a better choice than pentium4.
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if (triple.getEnvironment() == llvm::Triple::Android) {
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return "core2";
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// Fallback to p4.
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}
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return "pentium4";
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}
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static std::string getARMTargetCPU(const llvm::Triple &triple) {
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const char *result = llvm::StringSwitch<const char *>(triple.getArchName())
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.Cases("armv2", "armv2a", "arm2")
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.Case("armv3", "arm6")
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.Case("armv3m", "arm7m")
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.Case("armv4", "strongarm")
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.Case("armv4t", "arm7tdmi")
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.Cases("armv5", "armv5t", "arm10tdmi")
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.Cases("armv5e", "armv5te", "arm1026ejs")
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.Case("armv5tej", "arm926ej-s")
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.Cases("armv6", "armv6k", "arm1136jf-s")
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.Case("armv6j", "arm1136j-s")
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.Cases("armv6z", "armv6zk", "arm1176jzf-s")
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.Case("armv6t2", "arm1156t2-s")
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.Cases("armv6m", "armv6-m", "cortex-m0")
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.Cases("armv7", "armv7a", "armv7-a", "cortex-a8")
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.Cases("armv7l", "armv7-l", "cortex-a8")
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.Cases("armv7f", "armv7-f", "cortex-a9-mp")
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.Cases("armv7s", "armv7-s", "swift")
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.Cases("armv7r", "armv7-r", "cortex-r4")
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.Cases("armv7m", "armv7-m", "cortex-m3")
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.Cases("armv7em", "armv7e-m", "cortex-m4")
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.Cases("armv8", "armv8a", "armv8-a", "cortex-a53")
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.Case("ep9312", "ep9312")
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.Case("iwmmxt", "iwmmxt")
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.Case("xscale", "xscale")
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// If all else failed, return the most base CPU with
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// thumb interworking
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// supported by LLVM.
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.Default(nullptr);
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if (result) {
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return result;
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}
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return (triple.getEnvironment() == llvm::Triple::GNUEABIHF) ? "arm1176jzf-s"
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: "arm7tdmi";
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}
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/// Returns the LLVM name of the target CPU to use given the provided
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/// -mcpu argument and target triple.
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static std::string getTargetCPU(const std::string &cpu,
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const llvm::Triple &triple) {
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if (!cpu.empty()) {
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if (cpu != "native") {
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return cpu;
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}
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// FIXME: Reject attempts to use -mcpu=native unless the target matches
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// the host.
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std::string hostCPU = llvm::sys::getHostCPUName();
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if (!hostCPU.empty() && hostCPU != "generic") {
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return hostCPU;
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}
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}
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switch (triple.getArch()) {
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default:
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// We don't know about the specifics of this platform, just return the
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// empty string and let LLVM decide.
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return cpu;
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case llvm::Triple::x86:
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case llvm::Triple::x86_64:
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return getX86TargetCPU(triple);
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case llvm::Triple::arm:
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return getARMTargetCPU(triple);
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}
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}
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static const char *getLLVMArchSuffixForARM(llvm::StringRef CPU) {
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return llvm::StringSwitch<const char *>(CPU)
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.Case("strongarm", "v4")
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.Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "v4t")
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.Cases("arm720t", "arm9", "arm9tdmi", "v4t")
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.Cases("arm920", "arm920t", "arm922t", "v4t")
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.Cases("arm940t", "ep9312", "v4t")
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.Cases("arm10tdmi", "arm1020t", "v5")
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.Cases("arm9e", "arm926ej-s", "arm946e-s", "v5e")
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.Cases("arm966e-s", "arm968e-s", "arm10e", "v5e")
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.Cases("arm1020e", "arm1022e", "xscale", "iwmmxt", "v5e")
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.Cases("arm1136j-s", "arm1136jf-s", "arm1176jz-s", "v6")
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.Cases("arm1176jzf-s", "mpcorenovfp", "mpcore", "v6")
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.Cases("arm1156t2-s", "arm1156t2f-s", "v6t2")
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.Cases("cortex-a5", "cortex-a7", "cortex-a8", "v7")
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.Cases("cortex-a9", "cortex-a12", "cortex-a15", "v7")
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.Cases("cortex-r4", "cortex-r5", "v7r")
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.Case("cortex-m0", "v6m")
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.Case("cortex-m3", "v7m")
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.Case("cortex-m4", "v7em")
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.Case("cortex-a9-mp", "v7f")
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.Case("swift", "v7s")
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.Case("cortex-a53", "v8")
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.Case("krait", "v7")
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.Default("");
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}
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static FloatABI::Type getARMFloatABI(const llvm::Triple &triple,
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const char *llvmArchSuffix) {
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switch (triple.getOS()) {
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case llvm::Triple::Darwin:
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case llvm::Triple::MacOSX:
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case llvm::Triple::IOS: {
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// Darwin defaults to "softfp" for v6 and v7.
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if (llvm::StringRef(llvmArchSuffix).startswith("v6") ||
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llvm::StringRef(llvmArchSuffix).startswith("v7")) {
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return FloatABI::SoftFP;
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}
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return FloatABI::Soft;
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}
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case llvm::Triple::FreeBSD:
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// FreeBSD defaults to soft float
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return FloatABI::Soft;
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default:
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if (triple.getVendorName().startswith("hardfloat"))
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return FloatABI::Hard;
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if (triple.getVendorName().startswith("softfloat"))
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return FloatABI::SoftFP;
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switch (triple.getEnvironment()) {
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case llvm::Triple::GNUEABIHF:
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return FloatABI::Hard;
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case llvm::Triple::GNUEABI:
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return FloatABI::SoftFP;
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case llvm::Triple::EABI:
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// EABI is always AAPCS, and if it was not marked 'hard', it's softfp
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return FloatABI::SoftFP;
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case llvm::Triple::Android: {
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if (llvm::StringRef(llvmArchSuffix).startswith("v7")) {
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return FloatABI::SoftFP;
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}
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return FloatABI::Soft;
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}
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default:
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// Assume "soft".
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// TODO: Warn the user we are guessing.
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return FloatABI::Soft;
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}
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}
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}
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#if LDC_LLVM_VER < 307
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/// Sanitizes the MIPS ABI in the feature string.
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static void addMipsABI(const llvm::Triple &triple,
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std::vector<std::string> &attrs) {
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enum ABI { O32 = 1 << 0, N32 = 1 << 1, N64 = 1 << 2, EABI = 1 << 3 };
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const bool is64Bit = triple.getArch() == llvm::Triple::mips64 ||
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triple.getArch() == llvm::Triple::mips64el;
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const uint32_t defaultABI = is64Bit ? N64 : O32;
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uint32_t bits = defaultABI;
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auto I = attrs.begin();
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while (I != attrs.end()) {
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std::string str = *I;
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bool enabled = str[0] == '+';
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std::string flag = (str[0] == '+' || str[0] == '-') ? str.substr(1) : str;
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uint32_t newBit = 0;
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if (flag == "o32") {
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newBit = O32;
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}
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if (flag == "n32") {
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newBit = N32;
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}
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if (flag == "n64") {
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newBit = N64;
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}
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if (flag == "eabi") {
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newBit = EABI;
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}
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if (newBit) {
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I = attrs.erase(I);
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if (enabled) {
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bits |= newBit;
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} else {
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bits &= ~newBit;
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}
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} else {
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++I;
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}
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}
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switch (bits) {
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case O32:
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attrs.push_back("+o32");
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break;
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case N32:
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attrs.push_back("+n32");
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break;
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case N64:
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attrs.push_back("+n64");
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break;
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case EABI:
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attrs.push_back("+eabi");
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break;
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default:
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error(Loc(), "Only one ABI argument is supported");
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fatal();
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}
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if (bits != defaultABI) {
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attrs.push_back(is64Bit ? "-n64" : "-o32");
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}
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}
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#endif
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/// Looks up a target based on an arch name and a target triple.
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///
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/// If the arch name is non-empty, then the lookup is done by arch. Otherwise,
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/// the target triple is used.
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///
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/// This has been adapted from the corresponding LLVM 3.2+ overload of
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/// llvm::TargetRegistry::lookupTarget. Once support for LLVM 3.1 is dropped,
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/// the registry method can be used instead.
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const llvm::Target *lookupTarget(const std::string &arch, llvm::Triple &triple,
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std::string &errorMsg) {
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// Allocate target machine. First, check whether the user has explicitly
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// specified an architecture to compile for. If so we have to look it up by
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// name, because it might be a backend that has no mapping to a target triple.
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const llvm::Target *target = nullptr;
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if (!arch.empty()) {
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#if LDC_LLVM_VER >= 307
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for (const llvm::Target &T : llvm::TargetRegistry::targets()) {
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#else
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for (auto it = llvm::TargetRegistry::begin(),
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ie = llvm::TargetRegistry::end();
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it != ie; ++it) {
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const llvm::Target &T = *it;
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#endif
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if (arch == T.getName()) {
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target = &T;
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break;
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}
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}
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if (!target) {
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errorMsg = "invalid target architecture '" + arch +
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"', see "
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"-version for a list of supported targets.";
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return nullptr;
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}
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// Adjust the triple to match (if known), otherwise stick with the
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// given triple.
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const auto Type = llvm::Triple::getArchTypeForLLVMName(arch);
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if (Type != llvm::Triple::UnknownArch) {
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triple.setArch(Type);
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if (Type == llvm::Triple::x86)
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triple.setArchName("i686"); // instead of i386
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}
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} else {
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std::string tempError;
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target = llvm::TargetRegistry::lookupTarget(triple.getTriple(), tempError);
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if (!target) {
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errorMsg = "unable to get target for '" + triple.getTriple() +
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"', see -version and -mtriple.";
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}
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}
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return target;
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}
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llvm::TargetMachine *createTargetMachine(
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std::string targetTriple, std::string arch, std::string cpu,
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std::vector<std::string> attrs, ExplicitBitness::Type bitness,
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FloatABI::Type floatABI,
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#if LDC_LLVM_VER >= 309
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llvm::Optional<llvm::Reloc::Model> relocModel,
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#else
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llvm::Reloc::Model relocModel,
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#endif
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llvm::CodeModel::Model codeModel, llvm::CodeGenOpt::Level codeGenOptLevel,
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bool noFramePointerElim, bool noLinkerStripDead) {
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// Determine target triple. If the user didn't explicitly specify one, use
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// the one set at LLVM configure time.
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llvm::Triple triple;
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if (targetTriple.empty()) {
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triple = llvm::Triple(llvm::sys::getDefaultTargetTriple());
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// We only support OSX, so darwin should really be macosx.
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if (triple.getOS() == llvm::Triple::Darwin) {
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triple.setOS(llvm::Triple::MacOSX);
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}
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// Handle -m32/-m64.
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if (sizeof(void *) != 8 && bitness == ExplicitBitness::M64) {
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triple = triple.get64BitArchVariant();
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} else if (sizeof(void *) != 4 && bitness == ExplicitBitness::M32) {
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triple = triple.get32BitArchVariant();
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if (triple.getArch() == llvm::Triple::ArchType::x86)
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triple.setArchName("i686"); // instead of i386
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}
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} else {
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triple = llvm::Triple(llvm::Triple::normalize(targetTriple));
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}
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// Look up the LLVM backend to use. This also updates triple with the
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// user-specified arch, if any.
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std::string errMsg;
|
||
const llvm::Target *target = lookupTarget(arch, triple, errMsg);
|
||
if (target == nullptr) {
|
||
error(Loc(), "%s", errMsg.c_str());
|
||
fatal();
|
||
}
|
||
|
||
// Package up features to be passed to target/subtarget.
|
||
llvm::SubtargetFeatures features;
|
||
features.getDefaultSubtargetFeatures(triple);
|
||
if (cpu == "native") {
|
||
llvm::StringMap<bool> hostFeatures;
|
||
if (llvm::sys::getHostCPUFeatures(hostFeatures)) {
|
||
for (const auto &hf : hostFeatures) {
|
||
features.AddFeature(
|
||
std::string(hf.second ? "+" : "-").append(hf.first()));
|
||
}
|
||
}
|
||
}
|
||
#if LDC_LLVM_VER < 307
|
||
if (triple.getArch() == llvm::Triple::mips ||
|
||
triple.getArch() == llvm::Triple::mipsel ||
|
||
triple.getArch() == llvm::Triple::mips64 ||
|
||
triple.getArch() == llvm::Triple::mips64el) {
|
||
addMipsABI(triple, attrs);
|
||
}
|
||
#endif
|
||
for (auto &attr : attrs) {
|
||
features.AddFeature(attr);
|
||
}
|
||
|
||
// With an empty CPU string, LLVM will default to the host CPU, which is
|
||
// usually not what we want (expected behavior from other compilers is
|
||
// to default to "generic").
|
||
cpu = getTargetCPU(cpu, triple);
|
||
|
||
// cmpxchg16b is not available on old 64bit CPUs. Enable code generation
|
||
// if the user did not make an explicit choice.
|
||
if (cpu == "x86-64") {
|
||
const char *cx16_plus = "+cx16";
|
||
const char *cx16_minus = "-cx16";
|
||
bool cx16 = false;
|
||
for (auto &attr : attrs) {
|
||
if (attr == cx16_plus || attr == cx16_minus) {
|
||
cx16 = true;
|
||
}
|
||
}
|
||
if (!cx16) {
|
||
features.AddFeature(cx16_plus);
|
||
}
|
||
}
|
||
|
||
if (Logger::enabled()) {
|
||
Logger::println("Targeting '%s' (CPU '%s' with features '%s')",
|
||
triple.str().c_str(), cpu.c_str(),
|
||
features.getString().c_str());
|
||
}
|
||
|
||
// Handle cases where LLVM picks wrong default relocModel
|
||
#if LDC_LLVM_VER >= 309
|
||
if (!relocModel.hasValue()) {
|
||
#else
|
||
if (relocModel == llvm::Reloc::Default) {
|
||
#endif
|
||
if (triple.isOSDarwin()) {
|
||
// Darwin defaults to PIC (and as of 10.7.5/LLVM 3.1-3.3, TLS use leads
|
||
// to crashes for non-PIC code). LLVM doesn't handle this.
|
||
relocModel = llvm::Reloc::PIC_;
|
||
} else if (triple.isOSLinux()) {
|
||
// Modern Linux distributions have their toolchain generate PIC code for additional security
|
||
// features (like ASLR). We default to PIC code to avoid linking issues on these OSes.
|
||
// On Android, PIC is default as well.
|
||
relocModel = llvm::Reloc::PIC_;
|
||
} else {
|
||
// ARM for other than Darwin or Android defaults to static
|
||
switch (triple.getArch()) {
|
||
default:
|
||
break;
|
||
case llvm::Triple::arm:
|
||
case llvm::Triple::armeb:
|
||
case llvm::Triple::thumb:
|
||
case llvm::Triple::thumbeb:
|
||
relocModel = llvm::Reloc::Static;
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
|
||
if (floatABI == FloatABI::Default) {
|
||
switch (triple.getArch()) {
|
||
default: // X86, ...
|
||
floatABI = FloatABI::Hard;
|
||
break;
|
||
case llvm::Triple::arm:
|
||
case llvm::Triple::thumb:
|
||
floatABI = getARMFloatABI(triple, getLLVMArchSuffixForARM(cpu));
|
||
break;
|
||
}
|
||
}
|
||
|
||
llvm::TargetOptions targetOptions;
|
||
#if LDC_LLVM_VER < 307
|
||
targetOptions.NoFramePointerElim = noFramePointerElim;
|
||
#endif
|
||
#if LDC_LLVM_VER >= 307
|
||
targetOptions.MCOptions.ABIName = getABI(triple);
|
||
#endif
|
||
|
||
switch (floatABI) {
|
||
default:
|
||
llvm_unreachable("Floating point ABI type unknown.");
|
||
case FloatABI::Soft:
|
||
#if LDC_LLVM_VER < 307
|
||
targetOptions.UseSoftFloat = true;
|
||
#endif
|
||
targetOptions.FloatABIType = llvm::FloatABI::Soft;
|
||
break;
|
||
case FloatABI::SoftFP:
|
||
#if LDC_LLVM_VER < 307
|
||
targetOptions.UseSoftFloat = false;
|
||
#endif
|
||
targetOptions.FloatABIType = llvm::FloatABI::Soft;
|
||
break;
|
||
case FloatABI::Hard:
|
||
#if LDC_LLVM_VER < 307
|
||
targetOptions.UseSoftFloat = false;
|
||
#endif
|
||
targetOptions.FloatABIType = llvm::FloatABI::Hard;
|
||
break;
|
||
}
|
||
|
||
// Right now, we only support linker-level dead code elimination on Linux
|
||
// using the GNU toolchain (based on ld's --gc-sections flag). The Apple ld
|
||
// on OS X supports a similar flag (-dead_strip) that doesn't require
|
||
// emitting the symbols into different sections. The MinGW ld doesn't seem
|
||
// to support --gc-sections at all, and FreeBSD needs more investigation.
|
||
if (!noLinkerStripDead && (triple.getOS() == llvm::Triple::Linux ||
|
||
triple.getOS() == llvm::Triple::Win32)) {
|
||
targetOptions.FunctionSections = true;
|
||
targetOptions.DataSections = true;
|
||
}
|
||
|
||
return target->createTargetMachine(triple.str(), cpu, features.getString(),
|
||
targetOptions, relocModel, codeModel,
|
||
codeGenOptLevel);
|
||
}
|