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convert Freg numbers in instr.d
This commit is contained in:
Walter Bright
The Dlang Bot
parent
05bfa58b65
commit
fd8b00b58c
2 changed files with 42 additions and 34 deletions
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@ -1279,28 +1279,28 @@ else
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switch (e.Eoper)
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{
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case OPd_s16:
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cdb.gen1(INSTR.fcvtzs(0,ftype,V1 & 31,Rd)); // fcvtzs Rd,V1
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cdb.gen1(INSTR.fcvtzs(0,ftype,V1,Rd)); // fcvtzs Rd,V1
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cdb.gen1(INSTR.sxth_sbfm(0,Rd,Rd)); // sxth Rd,Rd
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break;
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case OPd_s32:
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cdb.gen1(INSTR.fcvtzs(0,1,V1 & 31,Rd)); // fcvtzs Rd,V1
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cdb.gen1(INSTR.fcvtzs(0,1,V1,Rd)); // fcvtzs Rd,V1
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break;
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case OPd_s64:
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cdb.gen1(INSTR.fcvtzs_asisdmisc(1,V1,V1)); // fcvtzs V1,V1
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,6,V1 & 31,Rd)); // fmov Rd,V1
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,6,V1,Rd)); // fmov Rd,V1
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break;
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case OPd_u16:
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cdb.gen1(INSTR.fcvtzu(0,ftype,V1 & 31,Rd)); // fcvtzu Rd,V1
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cdb.gen1(INSTR.fcvtzu(0,ftype,V1,Rd)); // fcvtzu Rd,V1
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uint N,immr,imms;
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assert(encodeNImmrImms(0xFFFF,N,immr,imms));
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cdb.gen1(INSTR.log_imm(0,0,0,immr,imms,Rd,Rd)); // and Rd,Rd,#0xFFFF
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break;
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case OPd_u32:
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cdb.gen1(INSTR.fcvtzu(0,1,V1 & 31,Rd)); // fcvtzu Rd,V1
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cdb.gen1(INSTR.fcvtzu(0,1,V1,Rd)); // fcvtzu Rd,V1
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break;
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case OPd_u64:
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cdb.gen1(INSTR.fcvtzu_asisdmisc(1,V1,V1)); // fcvtzu V1,V1
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,6,V1 & 31,Rd)); // fmov Rd,V1
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,6,V1,Rd)); // fmov Rd,V1
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break;
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default:
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assert(0);
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@ -1322,38 +1322,38 @@ else
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static if (1)
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{
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regm_t retregs = mCX; // hack because no floating support in rest of code
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reg_t Rd = CX;
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reg_t Vd = CX;
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}
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else
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{
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regm_t retregs = FLOATREGS;
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const tym = tybasic(e.Ety);
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reg_t Rd = allocreg(cdb,retregs,tym); // destination integer register
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reg_t Vd = allocreg(cdb,retregs,tym); // destination integer register
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}
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switch (e.Eoper)
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{
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case OPs16_d:
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cdb.gen1(INSTR.sxth_sbfm(0,R1,R1)); // sxth w0,w0
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cdb.gen1(INSTR.scvtf_float_int(0,1,Rd,R1)); // scvtf d31,w0
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cdb.gen1(INSTR.scvtf_float_int(0,1,Vd,R1)); // scvtf d31,w0
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break;
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case OPs32_d:
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cdb.gen1(INSTR.scvtf_float_int(0,1,Rd,R1)); // scvtf d31,w0
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cdb.gen1(INSTR.scvtf_float_int(0,1,Vd,R1)); // scvtf d31,w0
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break;
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case OPs64_d:
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cdb.gen1(INSTR.scvtf_float_int(1,1,Rd,R1)); // scvtf d31,x0
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cdb.gen1(INSTR.scvtf_float_int(1,1,Vd,R1)); // scvtf d31,x0
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break;
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case OPu16_d:
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/* not executed because OPu16_d was converted to OPu16_32 then OP32_d */
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uint N,immr,imms;
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assert(encodeNImmrImms(0xFFFF,N,immr,imms));
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cdb.gen1(INSTR.log_imm(0,0,0,immr,imms,R1,R1)); // and w0,w0,#0xFFFF
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cdb.gen1(INSTR.ucvtf_float_int(0,1,Rd,R1)); // ucvtf d31,w0
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cdb.gen1(INSTR.ucvtf_float_int(0,1,Vd,R1)); // ucvtf d31,w0
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break;
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case OPu32_d:
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cdb.gen1(INSTR.ucvtf_float_int(0,1,Rd,R1)); // ucvtf d31,w0
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cdb.gen1(INSTR.ucvtf_float_int(0,1,Vd,R1)); // ucvtf d31,w0
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break;
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case OPu64_d:
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cdb.gen1(INSTR.ucvtf_float_int(1,1,Rd,R1)); // ucvtf d31,x0
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cdb.gen1(INSTR.ucvtf_float_int(1,1,Vd,R1)); // ucvtf d31,x0
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break;
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default:
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assert(0);
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@ -39,7 +39,7 @@ struct INSTR
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{
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pure nothrow:
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/* Even though the floating point registers are V0..31, we call them 32-63 so they fit
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/* Even though the floating point registers are 0..31, we call them V32..V63 so they fit
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* into regm_t. Remember to and them with 31 to generate an instruction
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*/
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enum FLOATREGS = 0xFFFF_FFFF_0000_0000;
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@ -550,6 +550,7 @@ struct INSTR
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*/
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static uint asisdmisc(uint U, uint size, uint opcode, reg_t Rn, reg_t Rd)
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{
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assert(Rn < 32 && Rd < 32);
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uint ins = (1 << 30) |
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(U << 29) |
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(0x1E << 24) |
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@ -565,12 +566,12 @@ struct INSTR
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/* FCVTZS <V><d>,<V><n> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
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* Scalar single-precision and double-precision
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*/
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static uint fcvtzs_asisdmisc(uint sz, reg_t Rn, reg_t Rd) { return asisdmisc(0, 2|sz, 0x1B, Rn, Rd); }
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static uint fcvtzs_asisdmisc(uint sz, reg_t Vn, reg_t Vd) { return asisdmisc(0, 2|sz, 0x1B, Vn & 31, Vd & 31); }
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/* FCVTZU <V><d>,<V><n> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_advsimd_int.html
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* Scalar single-precision and double-precision
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*/
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static uint fcvtzu_asisdmisc(uint sz, reg_t Rn, reg_t Rd) { return asisdmisc(1, 2|sz, 0x1B, Rn, Rd); }
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static uint fcvtzu_asisdmisc(uint sz, reg_t Vn, reg_t Vd) { return asisdmisc(1, 2|sz, 0x1B, Vn & 31, Vd & 31); }
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/* Advanced SIMD scalar pairwise
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@ -592,6 +593,7 @@ struct INSTR
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*/
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static uint asimdmisc(uint Q, uint U, uint size, uint opcode, reg_t Rn, reg_t Rd)
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{
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assert(Rn < 32 && Rd < 32);
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uint ins = (0 << 31) |
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(Q << 30) |
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(U << 29) |
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@ -608,23 +610,24 @@ struct INSTR
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/* CNT <Vd>.<T>, <Vn>.<T>
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* https://www.scs.stanford.edu/~zyedidia/arm64/cnt_advsimd.html
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*/
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static uint cnt_advsimd(uint Q, uint size, reg_t Rn, reg_t Rd) { return asimdmisc(Q, 0, size, 5, Rn, Rd); }
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static uint cnt_advsimd(uint Q, uint size, reg_t Vn, reg_t Vd) { return asimdmisc(Q, 0, size, 5, Vn & 31, Vd & 31); }
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/* FCVTZS <Vd>.<T>,<Vn>.<T> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
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* Vector single-precision and double-precision
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*/
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static uint fcvtzs_asimdmisc(uint Q, uint sz, reg_t Rn, reg_t Rd) { return asimdmisc(Q, 0, 2|sz, 0x1B, Rn, Rd); }
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static uint fcvtzs_asimdmisc(uint Q, uint sz, reg_t Vn, reg_t Vd) { return asimdmisc(Q, 0, 2|sz, 0x1B, Vn & 31, Vd & 31); }
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/* FCVTZU <Vd>.<T>,<Vn>.<T> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_advsimd_int.html
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* Vector single-precision and double-precision
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*/
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static uint fcvtzu_asimdmisc(uint Q, uint sz, reg_t Rn, reg_t Rd) { return asimdmisc(Q, 1, 2|sz, 0x1B, Rn, Rd); }
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static uint fcvtzu_asimdmisc(uint Q, uint sz, reg_t Vn, reg_t Vd) { return asimdmisc(Q, 1, 2|sz, 0x1B, Vn & 31, Vd & 31); }
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/* Advanced SIMD across lanes
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* https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdall
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*/
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static uint asimdall(uint Q, uint U, uint size, uint opcode, reg_t Rn, reg_t Rd)
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{
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assert(Rn < 32 && Rd < 32);
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uint ins = (0 << 31) |
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(Q << 30) |
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(U << 29) |
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@ -640,11 +643,11 @@ struct INSTR
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/* ADDV <V><d>, <Vn>.<T> https://www.scs.stanford.edu/~zyedidia/arm64/addv_advsimd.html
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*/
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static uint addv_advsimd(uint Q, uint size, reg_t Rn, reg_t Rd) { return asimdall(Q, 0, size, 0x1B, Rn, Rd); }
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static uint addv_advsimd(uint Q, uint size, reg_t Vn, reg_t Vd) { return asimdall(Q, 0, size, 0x1B, Vn & 31, Vd & 31); }
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/* UADDLV <V><d>, <Vn>.<T> https://www.scs.stanford.edu/~zyedidia/arm64/uaddlv_advsimd.html
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*/
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static uint uaddlv_advsimd(uint Q, uint size, reg_t Rn, reg_t Rd) { return asimdall(Q, 1, size, 3, Rn, Rd); }
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static uint uaddlv_advsimd(uint Q, uint size, reg_t Vn, reg_t Vd) { return asimdall(Q, 1, size, 3, Vn & 31, Vd & 31); }
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/* Advanced SIMD three different
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* Advanced SIMD three same
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@ -655,7 +658,7 @@ struct INSTR
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*/
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// FMOV Rd, Rn https://www.scs.stanford.edu/~zyedidia/arm64/fmov_float.html
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static uint fmov(uint ftype, uint Rn, uint Rd) { return floatdp1(0,0,ftype,0,Rn,Rd); }
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static uint fmov(uint ftype, reg_t Vn, reg_t Vd) { return floatdp1(0,0,ftype,0,Vn & 31,Vd & 31); }
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/* Advanced SIMD shift by immediate
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* Advanced SIMD vector x indexed element
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@ -671,6 +674,7 @@ struct INSTR
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*/
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static uint float2int(uint sf, uint S, uint ftype, uint rmode, uint opcode, reg_t Rn, reg_t Rd)
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{
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assert(Rn < 32 && Rd < 32);
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return (sf << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (rmode << 19) | (opcode << 16) | (Rn << 5) | Rd;
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}
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@ -678,52 +682,56 @@ struct INSTR
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*/
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static uint fmov_float_gen(uint sf, uint ftype, uint rmode, uint opcode, reg_t Rn, reg_t Rd)
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{
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if (opcode == 7)
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Rd &= 31;
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else if (opcode == 6)
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Rn &= 31;
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return float2int(sf, 0, ftype, rmode, opcode, Rn, Rd);
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}
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/* FCVTNS (scalar) https://www.scs.stanford.edu/~zyedidia/arm64/fcvtns_float.html
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*/
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static uint fcvtns(uint sf, uint ftype, reg_t Rn, reg_t Rd)
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static uint fcvtns(uint sf, uint ftype, reg_t Vn, reg_t Rd)
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{
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return float2int(sf, 0, ftype, 0, 0, Rn, Rd);
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return float2int(sf, 0, ftype, 0, 0, Vn & 31, Rd);
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}
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/* FCVTNU (scalar) https://www.scs.stanford.edu/~zyedidia/arm64/fcvtnu_float.html
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*/
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static uint fcvtnu(uint sf, uint ftype, reg_t Rn, reg_t Rd)
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static uint fcvtnu(uint sf, uint ftype, reg_t Vn, reg_t Rd)
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{
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return float2int(sf, 0, ftype, 0, 1, Rn, Rd);
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return float2int(sf, 0, ftype, 0, 1, Vn & 31, Rd);
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}
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/* FCVTZS (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_float_int.html
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*/
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static uint fcvtzs(uint sf, uint ftype, reg_t Rn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 0, Rn, Rd); }
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static uint fcvtzs(uint sf, uint ftype, reg_t Vn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 0, Vn & 31, Rd); }
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/* FCVTZU (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_float_int.html
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*/
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static uint fcvtzu(uint sf, uint ftype, reg_t Rn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 1, Rn, Rd); }
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static uint fcvtzu(uint sf, uint ftype, reg_t Vn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 1, Vn & 31, Rd); }
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/* SCVTF (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/scvtf_float_int.html
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*/
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static uint scvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Rd) { return float2int(sf,0,ftype,0,2,Rn,Rd); }
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static uint scvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Vd) { return float2int(sf,0,ftype,0,2,Rn,Vd & 31); }
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/* UCVTF (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/ucvtf_float_int.html
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*/
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static uint ucvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Rd) { return float2int(sf,0,ftype,0,3,Rn,Rd); }
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static uint ucvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Vd) { return float2int(sf,0,ftype,0,3,Rn,Vd & 31); }
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/* Floating-point data-processing (1 source)
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* https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#floatdp1
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*/
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static uint floatdp1(uint M, uint S, uint ftype, uint opcode, uint Rn, uint Rd)
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static uint floatdp1(uint M, uint S, uint ftype, uint opcode, reg_t Rn, reg_t Rd)
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{
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assert(Rn < 32 && Rd < 32); // remember to convert R32-63 to 0-31
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assert(Rn < 32 && Rd < 32); // remember to convert V32..V63 to R0..R31
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return (M << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (opcode << 15) | (0x10 << 10) | (Rn << 5) | Rd;
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}
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/* FCVT fpreg,fpreg https://www.scs.stanford.edu/~zyedidia/arm64/fcvt_float.html
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*/
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static uint fcvt_float(uint ftype, uint opcode, reg_t Rn, reg_t Rd) { return floatdp1(0,0,ftype,opcode,Rn,Rd); }
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static uint fcvt_float(uint ftype, uint opcode, reg_t Vn, reg_t Vd) { return floatdp1(0,0,ftype,opcode,Vn & 31,Vd & 31); }
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/* Floating-point compare
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* Floating-point immediate
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