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add Arm conversions of double to integral (#20809)
This commit is contained in:
Walter Bright
GitHub
parent
be8668e938
commit
f9f4048aed
4 changed files with 154 additions and 227 deletions
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@ -655,12 +655,6 @@ void cddivass(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
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@trusted
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void cdshass(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
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{
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if (cg.AArch64)
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{
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import dmd.backend.arm.cod4 : cdshass;
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return cdshass(cg, cdb, e, pretregs);
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}
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//printf("cdshass(e=%p, pretregs = %s)\n",e,regm_str(pretregs));
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elem* e1 = e.E1;
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elem* e2 = e.E2;
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@ -1227,15 +1221,13 @@ ret:
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}
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// longcmp
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// cdcnvt
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/*****************************
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* Do conversions.
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* Do floating point conversions.
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* Depends on OPd_s32 and CLIB.dbllng being in sequence.
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OPvp_fp
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OPcvp_fp
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OPd_s32
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OPb_8
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OPs32_d
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OPd_s16
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OPs16_d
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@ -1254,212 +1246,67 @@ void cdcnvt(ref CGstate cg, ref CodeBuilder cdb,elem* e, ref regm_t pretregs)
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//printf("cdcnvt: %p pretregs = %s\n", e, regm_str(pretregs));
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//elem_print(e);
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assert(!e); // these are floating point conversions, do them later
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static immutable ubyte[2][16] clib =
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[
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[ OPd_s32, CLIB.dbllng ],
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[ OPs32_d, CLIB.lngdbl ],
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[ OPd_s16, CLIB.dblint ],
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[ OPs16_d, CLIB.intdbl ],
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[ OPd_u16, CLIB.dbluns ],
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[ OPu16_d, CLIB.unsdbl ],
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[ OPd_u32, CLIB.dblulng ],
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[ OPu32_d, CLIB.ulngdbl ],
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[ OPd_s64, CLIB.dblllng ],
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[ OPs64_d, CLIB.llngdbl ],
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[ OPd_u64, CLIB.dblullng ],
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[ OPu64_d, CLIB.ullngdbl ],
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[ OPd_f, CLIB.dblflt ],
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[ OPf_d, CLIB.fltdbl ],
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[ OPvp_fp, CLIB.vptrfptr ],
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[ OPcvp_fp, CLIB.cvptrfptr]
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];
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if (!pretregs)
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{
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codelem(cgstate,cdb,e.E1,pretregs,false);
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return;
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}
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regm_t retregs;
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if (config.inline8087)
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{
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uint sf;
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uint ftype;
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switch (e.Eoper)
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{
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case OPld_d:
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case OPd_ld:
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case OPd_s16: // fcvtzs w0,d31 // sxth w0,w0
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case OPd_s32: ftype = 1; sf = 0; goto L2; // fcvtzs w0,d31
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case OPd_s64: ftype = 1; sf = 1; goto L2; // fcvtzs d31,d31 // fmov x0,d31
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case OPd_u16: // fcvtzu w0,d31 // and w0,w0,#0xFFFF
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case OPd_u32: // fcvtzu w0,d31
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case OPd_u64: // fcvtzu d31,d31 // fmov x0,d31
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L2:
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regm_t retregs1 = ALLREGS; //INSTR.FLOATREGS;
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retregs1 = mCX; // hack because no floating support in rest of code
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// codelem(cgstate,cdb,e.E1,retregs1,false);
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const reg_t V1 = findreg(retregs1); // source floating point register
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regm_t retregs = pretregs & cg.allregs;
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if (retregs == 0)
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retregs = ALLREGS & cgstate.allregs;
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const tym = tybasic(e.Ety);
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reg_t Rd = allocreg(cdb,retregs,tym); // destination integer register
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switch (e.Eoper)
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{
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if (tycomplex(e.E1.Ety))
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{
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Lcomplex:
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regm_t retregsx = mST01 | (pretregs & mPSW);
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codelem(cgstate,cdb,e.E1, retregsx, false);
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fixresult_complex87(cdb, e, retregsx, pretregs);
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return;
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}
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regm_t retregsx = mST0 | (pretregs & mPSW);
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codelem(cgstate,cdb,e.E1, retregsx, false);
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fixresult87(cdb, e, retregsx, pretregs);
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return;
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}
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case OPf_d:
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case OPd_f:
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if (tycomplex(e.E1.Ety))
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goto Lcomplex;
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if (config.fpxmmregs && pretregs & XMMREGS)
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{
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xmmcnvt(cdb, e, pretregs);
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return;
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}
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/* if won't do us much good to transfer back and */
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/* forth between 8088 registers and 8087 registers */
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if (OTcall(e.E1.Eoper) && !(pretregs & cgstate.allregs))
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{
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retregs = regmask(e.E1.Ety, e.E1.E1.Ety);
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if (retregs & (mXMM1 | mXMM0 |mST01 | mST0)) // if return in ST0
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{
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codelem(cgstate,cdb,e.E1,pretregs,false);
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if (pretregs & mST0)
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note87(e, 0, 0);
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return;
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}
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else
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break;
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}
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goto Lload87;
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case OPs64_d:
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if (!I64)
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goto Lload87;
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goto case OPs32_d;
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case OPs32_d:
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if (config.fpxmmregs && pretregs & XMMREGS)
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{
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xmmcnvt(cdb, e, pretregs);
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return;
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}
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goto Lload87;
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case OPs16_d:
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case OPu16_d:
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Lload87:
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load87(cdb,e,0,pretregs,null,-1);
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return;
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case OPu32_d:
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if (I64 && config.fpxmmregs && pretregs & XMMREGS)
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{
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xmmcnvt(cdb,e,pretregs);
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return;
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}
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else if (!I16)
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{
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regm_t retregsx = ALLREGS;
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codelem(cgstate,cdb,e.E1, retregsx, false);
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reg_t reg = findreg(retregsx);
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cdb.genfltreg(STO, reg, 0);
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reg = regwithvalue(cdb,ALLREGS,0,0);
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cdb.genfltreg(STO, reg, 4);
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push87(cdb);
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cdb.genfltreg(0xDF,5,0); // FILD m64int
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regm_t retregsy = mST0 /*| (pretregs & mPSW)*/;
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fixresult87(cdb, e, retregsy, pretregs);
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return;
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}
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break;
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case OPd_s64:
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if (!I64)
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goto Lcnvt87;
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goto case OPd_s32;
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case OPd_s16:
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case OPd_s32:
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if (config.fpxmmregs)
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{
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xmmcnvt(cdb,e,pretregs);
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return;
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}
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goto Lcnvt87;
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case OPd_u16:
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Lcnvt87:
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cnvt87(cdb,e,pretregs);
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return;
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case OPd_u32: // use subroutine, not 8087
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if (I64 && config.fpxmmregs)
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{
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xmmcnvt(cdb,e,pretregs);
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return;
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}
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if (I32 || I64)
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{
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cdd_u32(cdb,e,pretregs);
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return;
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}
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if (config.exe & EX_posix)
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{
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retregs = mST0;
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}
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else
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{
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retregs = DOUBLEREGS;
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}
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goto L1;
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case OPd_u64:
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if (I32 || I64)
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{
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cdd_u64(cdb,e,pretregs);
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return;
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}
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retregs = DOUBLEREGS;
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goto L1;
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case OPu64_d:
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if (pretregs & mST0)
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{
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regm_t retregsx = I64 ? mAX : mAX|mDX;
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codelem(cgstate,cdb,e.E1,retregsx,false);
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callclib(cdb,e,CLIB.u64_ldbl,pretregs,0);
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return;
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}
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cdb.gen1(INSTR.fcvtzs(0,ftype,V1 & 31,Rd)); // fcvtzs Rd,V1
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cdb.gen1(INSTR.sxth_sbfm(0,Rd,Rd)); // sxth Rd,Rd
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break;
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case OPd_s32:
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cdb.gen1(INSTR.fcvtzs(0,1,V1 & 31,Rd)); // fcvtzs Rd,V1
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break;
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case OPd_s64:
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cdb.gen1(INSTR.fcvtzs(1,1,V1,V1)); // fcvtzs V1,V1
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,V1 & 31,Rd)); // fmov Rd,V1
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break;
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case OPd_u16:
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cdb.gen1(INSTR.fcvtzu(0,ftype,V1 & 31,Rd)); // fcvtzu Rd,V1
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cdb.gen1(INSTR.sxth_sbfm(0,Rd,Rd)); // and Rd,Rd,#0xFFFF
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break;
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case OPd_u32:
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cdb.gen1(INSTR.fcvtzu(0,1,V1 & 31,Rd)); // fcvtzu Rd,V1
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break;
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case OPd_u64:
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cdb.gen1(INSTR.fcvtzu(1,1,V1,V1)); // fcvtzu V1,V1
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,V1 & 31,Rd)); // fmov Rd,V1
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break;
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default:
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assert(0);
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}
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case OPld_u64:
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{
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if (I32 || I64)
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{
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cdd_u64(cdb,e,pretregs);
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return;
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}
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regm_t retregsx = mST0;
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codelem(cgstate,cdb,e.E1,retregsx,false);
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callclib(cdb,e,CLIB.ld_u64,pretregs,0);
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return;
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}
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fixresult(cdb,e,retregs,pretregs);
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break;
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default:
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break;
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}
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}
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retregs = regmask(e.E1.Ety, TYnfunc);
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L1:
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codelem(cgstate,cdb,e.E1,retregs,false);
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for (int i = 0; 1; i++)
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{
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assert(i < clib.length);
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if (clib[i][0] == e.Eoper)
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{
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callclib(cdb,e,clib[i][1],pretregs,0);
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break;
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}
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assert(0);
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}
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}
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@ -1941,9 +1788,10 @@ void cdpopcnt(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
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const R1 = findreg(retregs1); // source register
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regm_t vregs = ALLREGS; // floating point register
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regm_t vregs = INSTR.FLOATREGS; // possible floating point registers
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reg_t Vx = allocreg(cdb, vregs, TYdouble);
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Vx &= 31; // to AArch64 register number
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cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,R1,Vx)); // FMOV Dx,X1
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cdb.gen1(INSTR.cnt_advsimd(0,0,Vx,Vx)); // CNT Vx.8b,Vx.8b
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cdb.gen1(INSTR.addv_advsimd(0,0,Vx,Vx)); // ADDV Bx,Vx.8b
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@ -1799,35 +1799,25 @@ void disassemble(uint c) @trusted
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// Advanced SIMD scalar three same FP16 https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdsamefp16
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// Advanced SIMD scalar two-register miscellaneous FP16 https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdmiscfp16
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// Advanced SIMD scalar three same extra https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdsame2
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// Advanced SIMD two-register miscellaneous http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdmisc
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if (field(ins,31,31) == 0 && field(ins,28,24) == 0x0E && field(ins,21,17) == 0x10 && field(ins,11,10) == 2)
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// Advanced SIMD scalar two-register miscellaneous http://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdmisc
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if (field(ins,31,30) == 1 && field(ins,28,24) == 0x1E && field(ins,21,17) == 0x10 && field(ins,11,10) == 2)
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{
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url = "asisdmisc";
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uint Q = field(ins,30,30);
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uint U = field(ins,29,29);
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uint size = field(ins,23,22);
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uint opcode = field(ins,16,12);
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uint Rn = field(ins, 9, 5);
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uint Rd = field(ins, 4, 0);
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//printf("ins:%08x Q:%d U:%d size:%d opcode:%x Rn:%d Rd:%d\n", ins, Q, U, size, opcode, Rn, Rd);
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if (U == 0 && size == 0 && opcode == 0x05) // https://www.scs.stanford.edu/~zyedidia/arm64/cnt_advsimd.html
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{
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p1 = "cnt"; // cnt <Vd>.<T>, <Vn>.<T>
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p2 = vregString(rbuf[0 .. 7], Q, Rd);
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p3 = vregString(rbuf[8 .. 14], Q, Rn);
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//printf("p2: %.*s p3: %.*s\n", cast(int)p2.length, p2.ptr, cast(int)p3.length, p3.ptr);
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}
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else if (U == 0 && (size & 2) && opcode == 0x1B) // https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
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{
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p1 = "fcvtzs";
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if (size & 2 && opcode == 0x1B) // https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
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{ // https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_advsimd_int.html
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p1 = U == 0 ? "fcvtzs" // fcvtzs <V><d>, <V><n> Scalar single-precision and double-precision
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: "fcvtzu"; // fcvtzu <V><d>, <V><n> Scalar single-precision and double-precision
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p2 = fregString(rbuf[0 .. 4],"sd h"[size & 1],Rd);
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p3 = fregString(rbuf[4 .. 8],"sd h"[size & 1],Rn);
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}
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}
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else
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// Advanced SIMD scalar pairwise https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdpair
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// Advanced SIMD scalar three different https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisddiff
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// Advanced SIMD scalar three same https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdsame
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@ -1840,7 +1830,41 @@ void disassemble(uint c) @trusted
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// Advanced SIMD three same (FP16) https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdsamefp16
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// Advanced SIMD two-register miscellaneous (FP16) https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdmiscfp16
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// Advanced SIMD three-register extension https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdsame2
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// Advanced SIMD two-register miscellaneous https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdmisc
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if (field(ins,31,31) == 0 && field(ins,28,24) == 0x0E && field(ins,21,17) == 0x10 && field(ins,11,10) == 2)
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{
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url = "asimdmisc";
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uint Q = field(ins,30,30);
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uint U = field(ins,29,29);
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uint size = field(ins,23,22);
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uint opcode = field(ins,16,12);
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uint Rn = field(ins, 9, 5);
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uint Rd = field(ins, 4, 0);
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//printf("ins:%08x Q:%d U:%d size:%d opcode:%x Rn:%d Rd:%d\n", ins, Q, U, size, opcode, Rn, Rd);
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immutable string[4] sizeQ = ["2S","4S","","2D"];
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if (U == 0 && size == 0 && opcode == 0x05) // https://www.scs.stanford.edu/~zyedidia/arm64/cnt_advsimd.html
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{
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p1 = "cnt"; // cnt <Vd>.<T>, <Vn>.<T>
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p2 = vregString(rbuf[0 .. 7], Q, Rd);
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p3 = vregString(rbuf[8 .. 14], Q, Rn);
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//printf("p2: %.*s p3: %.*s\n", cast(int)p2.length, p2.ptr, cast(int)p3.length, p3.ptr);
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}
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else if ((size & 2) && opcode == 0x1B) // https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
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{ // https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_advsimd_int.html
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p1 = U == 0 ? "fcvtzs" // fcvtzs <Vd>.<T>, <Vn>.<T> Vector single-precision and double-precision
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: "fcvtzu"; // fcvtzu <Vd>.<T>, <Vn>.<T> Vector single-precision and double-precision
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uint n = snprintf(rbuf.ptr, 7, "v%d.%s", Rd, sizeQ[(size & 1) * 2 + Q].ptr);
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p2 = buf[0 .. n];
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uint m = snprintf(rbuf.ptr + 7, 7, "v%d.%s", Rn, sizeQ[(size & 1) * 2 + Q].ptr);
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p3 = buf[7 .. 7 + m];
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}
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}
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else
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// Advanced SIMD across lanes https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdall
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if (field(ins,31,31) == 0 &&
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field(ins,28,24) == 0x0E &&
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|
|
@ -1939,9 +1963,9 @@ void disassemble(uint c) @trusted
|
|||
p2 = regString(sf,Rd);
|
||||
p3 = fregString(rbuf[4 .. 8],"sd h"[ftype],Rn);
|
||||
}
|
||||
else if (rmode == 3 && opcode == 0)
|
||||
else if (rmode == 3 && (opcode & ~1) == 0)
|
||||
{
|
||||
p1 = "fcvtzs";
|
||||
p1 = opcode ? "fcnvtzu" : "fcvtzs";
|
||||
p2 = regString(sf,Rd);
|
||||
p3 = fregString(rbuf[4 .. 8],"sd h"[ftype],Rn);
|
||||
}
|
||||
|
|
@ -2015,6 +2039,7 @@ void disassemble(uint c) @trusted
|
|||
p1 = ""; // no support half-float literals
|
||||
p3 = doubletostring(f);
|
||||
}
|
||||
else
|
||||
|
||||
// Floating-point conditional compare
|
||||
|
||||
|
|
@ -2773,8 +2798,9 @@ unittest
|
|||
unittest
|
||||
{
|
||||
int line64 = __LINE__;
|
||||
string[66] cases64 = // 64 bit code gen
|
||||
string[67] cases64 = // 64 bit code gen
|
||||
[
|
||||
"5E E1 BB FE fcvtzs d30,d31",
|
||||
"0E 31 BB FF addv b31,v31.8b",
|
||||
"2E 30 38 00 uaddlv h0,v0.8b",
|
||||
"0E 20 58 00 cnt v0.8b,v0.8b",
|
||||
|
|
|
|||
|
|
@ -39,6 +39,11 @@ struct INSTR
|
|||
{
|
||||
pure nothrow:
|
||||
|
||||
/* Even though the floating point registers are V0..31, we call them 32-63 so they fit
|
||||
* into regm_t. Remember to and them with 31 to generate an instruction
|
||||
*/
|
||||
enum FLOATREGS = 0xFFFF_FFFF_0000_0000;
|
||||
|
||||
enum uint nop = 0xD503201F;
|
||||
|
||||
alias reg_t = ubyte;
|
||||
|
|
@ -538,8 +543,37 @@ struct INSTR
|
|||
* Advanced SIMD scalar three same FP16
|
||||
* Advanced SIMD scalar two-register miscellaneous FP16
|
||||
* Advanced SIMD scalar three same extra
|
||||
* Advanced SIMD scalar two-register miscellaneous
|
||||
* Advanced SIMD scalar pairwise
|
||||
*/
|
||||
|
||||
/* Advanced SIMD scalar two-register miscellaneous
|
||||
* https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asisdmisc
|
||||
*/
|
||||
static uint asisdmisc(uint U, uint size, uint opcode, reg_t Rn, reg_t Rd)
|
||||
{
|
||||
uint ins = (1 << 30) |
|
||||
(U << 29) |
|
||||
(0x1E << 24) |
|
||||
(size << 22) |
|
||||
(0x10 << 17) |
|
||||
(opcode << 12) |
|
||||
(2 << 10) |
|
||||
(Rn << 5) |
|
||||
Rd;
|
||||
return ins;
|
||||
}
|
||||
|
||||
/* FCVTZS <V><d>,<V><n> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
|
||||
* Scalar single-precision and double-precision
|
||||
*/
|
||||
static uint fcvtzs_asisdmisc(uint sz, reg_t Rn, reg_t Rd) { return asisdmisc(0, 2|sz, 0x1B, Rn, Rd); }
|
||||
|
||||
/* FCVTZU <V><d>,<V><n> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_advsimd_int.html
|
||||
* Scalar single-precision and double-precision
|
||||
*/
|
||||
static uint fcvtzu_asisdmisc(uint sz, reg_t Rn, reg_t Rd) { return asisdmisc(1, 2|sz, 0x1B, Rn, Rd); }
|
||||
|
||||
|
||||
/* Advanced SIMD scalar pairwise
|
||||
* Advanced SIMD scalar three different
|
||||
* Advanced SIMD scalar three same
|
||||
* Advanced SIMD scalar shift by immediate
|
||||
|
|
@ -576,6 +610,16 @@ struct INSTR
|
|||
*/
|
||||
static uint cnt_advsimd(uint Q, uint size, reg_t Rn, reg_t Rd) { return asimdmisc(Q, 0, size, 5, Rn, Rd); }
|
||||
|
||||
/* FCVTZS <Vd>.<T>,<Vn>.<T> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_advsimd_int.html
|
||||
* Vector single-precision and double-precision
|
||||
*/
|
||||
static uint fcvtzs_asimdmisc(uint Q, uint sz, reg_t Rn, reg_t Rd) { return asimdmisc(Q, 0, 2|sz, 0x1B, Rn, Rd); }
|
||||
|
||||
/* FCVTZU <Vd>.<T>,<Vn>.<T> https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_advsimd_int.html
|
||||
* Vector single-precision and double-precision
|
||||
*/
|
||||
static uint fcvtzu_asimdmisc(uint Q, uint sz, reg_t Rn, reg_t Rd) { return asimdmisc(Q, 1, 2|sz, 0x1B, Rn, Rd); }
|
||||
|
||||
/* Advanced SIMD across lanes
|
||||
* https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#asimdall
|
||||
*/
|
||||
|
|
@ -623,7 +667,7 @@ struct INSTR
|
|||
* Conversion between floating-point and fixed-point
|
||||
*/
|
||||
|
||||
/* Converstion between floating-point and integer https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#float2int
|
||||
/* Conversion between floating-point and integer https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#float2int
|
||||
*/
|
||||
static uint float2int(uint sf, uint S, uint ftype, uint rmode, uint opcode, reg_t Rn, reg_t Rd)
|
||||
{
|
||||
|
|
@ -651,6 +695,14 @@ struct INSTR
|
|||
return float2int(sf, 0, ftype, 0, 1, Rn, Rd);
|
||||
}
|
||||
|
||||
/* FCVTZS (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzs_float_int.html
|
||||
*/
|
||||
static uint fcvtzs(uint sf, uint ftype, reg_t Rn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 0, Rn, Rd); }
|
||||
|
||||
/* FCVTZU (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/fcvtzu_float_int.html
|
||||
*/
|
||||
static uint fcvtzu(uint sf, uint ftype, reg_t Rn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 1, Rn, Rd); }
|
||||
|
||||
/* Floating-point data-processing (1 source)
|
||||
* https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#floatdp1
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -3216,6 +3216,7 @@ ret:
|
|||
@trusted
|
||||
void longcmp(ref CodeBuilder cdb, elem* e, bool jcond, FL fltarg, code* targ)
|
||||
{
|
||||
assert(!cgstate.AArch64);
|
||||
// <= > < >=
|
||||
static immutable ubyte[4] jopmsw = [JL, JG, JL, JG ];
|
||||
static immutable ubyte[4] joplsw = [JBE, JA, JB, JAE ];
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue