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redundate add of Voffset, disassembler correction (#21128)

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Walter Bright 2025-03-31 15:57:54 -07:00 • committed by GitHub
parent 4d0934d37f
commit bd670444c7
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3 changed files with 10 additions and 5 deletions
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4
compiler/src/dmd/backend/arm/cod1.d
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@ -108,7 +108,7 @@ void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
else if (cs.base != NOREG) else if (cs.base != NOREG)
{ {
// LDRB/LDRH/LDR reg,[cs.base, #offset] // LDRB/LDRH/LDR reg,[cs.base, #offset]
uint offset = cast(uint)cs.IEV1.Voffset; uint offset = 0; //cast(uint)cs.IEV1.Voffset; Voffset is added in by assignaddrc()
if (szr == 1) if (szr == 1)
cs.Iop = signExtend ? INSTR.ldrsb_imm(szw == 8, reg, cs.base, offset) cs.Iop = signExtend ? INSTR.ldrsb_imm(szw == 8, reg, cs.base, offset)
: INSTR.ldrb_imm (szw == 8, reg, cs.base, offset); : INSTR.ldrb_imm (szw == 8, reg, cs.base, offset);
@ -180,7 +180,7 @@ void storeToEA(ref code cs, reg_t reg, uint sz)
else if (cs.base != NOREG) else if (cs.base != NOREG)
{ {
// STRB/STRH/STR reg,[cs.base, #0] // STRB/STRH/STR reg,[cs.base, #0]
uint offset = cast(uint)cs.IEV1.Voffset; uint offset = 0; //cast(uint)cs.IEV1.Voffset; Voffset added in by assignaddr()
if (sz == 1) if (sz == 1)
cs.Iop = INSTR.strb_imm(reg, cs.base, offset); cs.Iop = INSTR.strb_imm(reg, cs.base, offset);
else if (sz == 2) else if (sz == 2)

2
compiler/src/dmd/backend/arm/cod2.d
View file

@ -1011,7 +1011,7 @@ void cdshift(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
uint opcode; uint opcode;
switch (e.Eoper) switch (e.Eoper)
{ {
case OPshl: opcode = 0x8; break; case OPshl: opcode = 0x8; break; // LSL Rd,Rn,Rm https://www.scs.stanford.edu/~zyedidia/arm64/lsl_lslv.html
case OPshr: opcode = 0x9; break; case OPshr: opcode = 0x9; break;
case OPashr: opcode = 0xA; break; case OPashr: opcode = 0xA; break;
case OPror: opcode = 0xB; break; case OPror: opcode = 0xB; break;

9
compiler/src/dmd/backend/arm/disasmarm.d
View file

@ -2237,8 +2237,13 @@ void disassemble(uint c) @trusted
bool is64 = false; bool is64 = false;
switch (ldr(size, VR, opc)) switch (ldr(size, VR, opc))
{ {
case ldr(0,0,0): p1 = "strb"; goto Lldr; case ldr(0,0,0): p1 = "strb"; goto Lldr8; // https://www.scs.stanford.edu/~zyedidia/arm64/strb_imm.html
case ldr(0,0,1): p1 = "ldrb"; goto Lldr; case ldr(0,0,1): p1 = "ldrb"; goto Lldr8;
Lldr8:
p2 = regString(is64, Rt);
p3 = eaString(0, cast(ubyte)Rn, imm12);
break;
case ldr(0,0,2): p1 = "ldrsb"; goto Lldr64; case ldr(0,0,2): p1 = "ldrsb"; goto Lldr64;
case ldr(0,0,3): p1 = "ldrsb"; goto Lldr; case ldr(0,0,3): p1 = "ldrsb"; goto Lldr;
case ldr(1,0,0): p1 = "strh"; goto Lldr; case ldr(1,0,0): p1 = "strh"; goto Lldr;