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add fpregs to loadFromEA() and storeToEA() (#20834)

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Walter Bright 2025-02-07 00:32:03 -08:00 • committed by GitHub
parent e6d09ab2a9
commit 2489ab7f7a
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3 changed files with 65 additions and 2 deletions
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51
compiler/src/dmd/backend/arm/cod1.d
View file

@ -55,6 +55,31 @@ nothrow:
*/ */
void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr) void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
{ {
if (reg & 32) // if floating point register
{
if (cs.reg != NOREG)
{
if (cs.reg != reg) // do not mov onto itself
{
assert(cs.reg & 32);
cs.Iop = INSTR.fmov(szw == 8,cs.reg,reg); // FMOV reg,cs.reg
}
}
else if (cs.base != NOREG)
{
// LDR reg,[cs.base, #offset]
assert(cs.index == NOREG);
uint imm12 = cs.Sextend;
if (szw == 4) imm12 >>= 2;
else if (szw == 8) imm12 >>= 3;
else assert(0);
cs.Iop = INSTR.ldr_imm_fpsimd(szw == 8 ? 3 : 2,1,imm12,cs.base,reg);
}
else
assert(0);
return;
}
if (cs.reg != NOREG) if (cs.reg != NOREG)
{ {
if (cs.reg != reg) // do not mov onto itself if (cs.reg != reg) // do not mov onto itself
@ -94,6 +119,32 @@ void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
*/ */
void storeToEA(ref code cs, reg_t reg, uint sz) void storeToEA(ref code cs, reg_t reg, uint sz)
{ {
if (reg & 32) // if floating point store
{
if (cs.reg != NOREG)
{
if (cs.reg != reg) // do not mov onto itself
{
assert(cs.reg & 32);
cs.Iop = INSTR.fmov(sz == 8,reg,cs.reg); // FMOV cs.reg,reg
}
cs.IFL1 = FL.unde;
}
else if (cs.base != NOREG)
{
// STR reg,[cs.base, #offset]
assert(cs.index == NOREG);
uint imm12 = cs.Sextend;
if (sz == 4) imm12 >>= 4;
else if (sz == 8) imm12 >>= 8;
else assert(0);
cs.Iop = INSTR.str_imm_fpsimd(sz == 8 ? 3 : 2,0,imm12,cs.base,reg);
}
else
assert(0);
return;
}
if (cs.reg != NOREG) if (cs.reg != NOREG)
{ {
if (cs.reg != reg) // do not mov onto itself if (cs.reg != reg) // do not mov onto itself

5
compiler/src/dmd/backend/arm/instr.d
View file

@ -926,6 +926,11 @@ struct INSTR
*/ */
static uint str_imm_fpsimd(uint size, uint opc, uint imm12, reg_t Rn, reg_t Vt) { return ldst_pos(size,1,opc,imm12,Rn,Vt); } static uint str_imm_fpsimd(uint size, uint opc, uint imm12, reg_t Rn, reg_t Vt) { return ldst_pos(size,1,opc,imm12,Rn,Vt); }
/* https://www.scs.stanford.edu/~zyedidia/arm64/ldr_imm_fpsimd.html
* LDR <Vt>,[<Xn|SP>,#<simm>] Unsigned offset
*/
static uint ldr_imm_fpsimd(uint size, uint opc, uint imm12, reg_t Rn, reg_t Vt) { return ldst_pos(size,1,opc,imm12,Rn,Vt); }
/* } */ /* } */
/* { ************************** Data Processing -- Register **********************************/ /* { ************************** Data Processing -- Register **********************************/

11
compiler/src/dmd/backend/x86/cod3.d
View file

@ -4299,12 +4299,19 @@ void prolog_loadparams(ref CodeBuilder cdb, tym_t tyf, bool pushalloc)
{ {
if (AArch64) if (AArch64)
{ {
uint imm = cast(uint)(offset + localsize + 16);
if (tyfloating(t.Tty)) if (tyfloating(t.Tty))
{
// STR preg,[bp,#offset] // STR preg,[bp,#offset]
cdb.gen1(INSTR.str_imm_fpsimd(2 + (sz == 8),0,cast(uint)(offset + localsize + 16) >> 3,29,preg)); if (sz == 8)
imm >>= 3;
else if (sz == 4)
imm >>= 2;
cdb.gen1(INSTR.str_imm_fpsimd(2 + (sz == 8),0,imm,29,preg));
}
else else
// STR preg,bp,#offset // STR preg,bp,#offset
cdb.gen1(INSTR.str_imm_gen(sz > 4, preg, 29, offset + localsize + 16)); cdb.gen1(INSTR.str_imm_gen(sz > 4, preg, 29, imm));
} }
else else
{ {