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operands reversed in float conversions (#21145)

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Walter Bright 2025-04-04 16:11:17 -07:00 • committed by GitHub
parent 14ec3e1c36
commit 22ce24ea07
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2 changed files with 16 additions and 13 deletions
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20
compiler/src/dmd/backend/arm/cod4.d
View file

@ -1406,36 +1406,36 @@ void cdcnvt(ref CGstate cg, ref CodeBuilder cdb,elem* e, ref regm_t pretregs)
case OPu64_d: // ucvtf d31,x0
regm_t retregs1 = ALLREGS;
codelem(cgstate,cdb,e.E1,retregs1,false);
reg_t R1 = findreg(retregs1);
reg_t Rn = findreg(retregs1); // source integer register
regm_t retregs = INSTR.FLOATREGS;
const tym = tybasic(e.Ety);
reg_t Vd = allocreg(cdb,retregs,tym); // destination integer register
reg_t Vd = allocreg(cdb,retregs,tym); // destination floating register
switch (e.Eoper)
{
case OPs16_d:
cdb.gen1(INSTR.sxth_sbfm(0,R1,R1)); // sxth w0,w0
cdb.gen1(INSTR.scvtf_float_int(0,1,Vd,R1)); // scvtf d31,w0
cdb.gen1(INSTR.sxth_sbfm(0,Rn,Rn)); // sxth w0,w0
cdb.gen1(INSTR.scvtf_float_int(0,1,Rn,Vd)); // scvtf d31,w0
break;
case OPs32_d:
cdb.gen1(INSTR.scvtf_float_int(0,1,Vd,R1)); // scvtf d31,w0
cdb.gen1(INSTR.scvtf_float_int(0,1,Rn,Vd)); // scvtf d31,w0
break;
case OPs64_d:
cdb.gen1(INSTR.scvtf_float_int(1,1,Vd,R1)); // scvtf d31,x0
cdb.gen1(INSTR.scvtf_float_int(1,1,Rn,Vd)); // scvtf d31,x0
break;
case OPu16_d:
/* not executed because OPu16_d was converted to OPu16_32 then OP32_d */
uint N,immr,imms;
assert(encodeNImmrImms(0xFFFF,N,immr,imms));
cdb.gen1(INSTR.log_imm(0,0,0,immr,imms,R1,R1)); // and w0,w0,#0xFFFF
cdb.gen1(INSTR.ucvtf_float_int(0,1,Vd,R1)); // ucvtf d31,w0
cdb.gen1(INSTR.log_imm(0,0,0,immr,imms,Rn,Rn)); // and w0,w0,#0xFFFF
cdb.gen1(INSTR.ucvtf_float_int(0,1,Rn,Vd)); // ucvtf d31,w0
break;
case OPu32_d:
cdb.gen1(INSTR.ucvtf_float_int(0,1,Vd,R1)); // ucvtf d31,w0
cdb.gen1(INSTR.ucvtf_float_int(0,1,Rn,Vd)); // ucvtf d31,w0
break;
case OPu64_d:
cdb.gen1(INSTR.ucvtf_float_int(1,1,Vd,R1)); // ucvtf d31,x0
cdb.gen1(INSTR.ucvtf_float_int(1,1,Rn,Vd)); // ucvtf d31,x0
break;
default:
assert(0);

9
compiler/src/dmd/backend/arm/instr.d
View file

@ -699,7 +699,8 @@ struct INSTR
*/
static uint float2int(uint sf, uint S, uint ftype, uint rmode, uint opcode, reg_t Rn, reg_t Rd)
{
assert(Rn < 32 && Rd < 32);
assert(Rd < 32);
assert(Rn < 32);
return (sf << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (rmode << 19) | (opcode << 16) | (Rn << 5) | Rd;
}
@ -737,12 +738,14 @@ struct INSTR
static uint fcvtzu(uint sf, uint ftype, reg_t Vn, reg_t Rd) { return float2int(sf, 0, ftype, 3, 1, Vn & 31, Rd); }
/* SCVTF (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/scvtf_float_int.html
* SCVTF Vd,Rn // integer to floating point
*/
static uint scvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Vd) { return float2int(sf,0,ftype,0,2,Rn,Vd & 31); }
static uint scvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Vd) { assert(Rn < 32 && Vd >= 32); return float2int(sf,0,ftype,0,2,Rn,Vd & 31); }
/* UCVTF (scalar, integer) https://www.scs.stanford.edu/~zyedidia/arm64/ucvtf_float_int.html
* UCVTF Vd,Rn // integer to floating point
*/
static uint ucvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Vd) { return float2int(sf,0,ftype,0,3,Rn,Vd & 31); }
static uint ucvtf_float_int(uint sf, uint ftype, reg_t Rn, reg_t Vd) { assert(Rn < 32 && Vd >= 32); return float2int(sf,0,ftype,0,3,Rn,Vd & 31); }
/* Floating-point data-processing (1 source)