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AArch64 OPd_f and OPf_d conversions (#20815)
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3 changed files with 43 additions and 2 deletions
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@ -1362,6 +1362,43 @@ else
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fixresult(cdb,e,retregs,pretregs);
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break;
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case OPd_f: // fcvt d31,s31
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case OPf_d: // fcvt s31,d31
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regm_t retregs1 = ALLREGS; //INSTR.FLOATREGS;
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static if (1)
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retregs1 = mCX; // hack because no floating support in rest of code
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else
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codelem(cgstate,cdb,e.E1,retregs1,false);
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const reg_t V1 = findreg(retregs1); // source floating point register
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static if (1)
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{
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regm_t retregs = mDX;
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}
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else
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{
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regm_t retregs = pretregs & INSTR.FLOATREGS;
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if (retregs == 0)
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retregs = INSTR.FLOATREGS & cgstate.allregs;
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}
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const tym = tybasic(e.Ety);
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reg_t Vd = allocreg(cdb,retregs,tym); // destination integer register
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switch (e.Eoper)
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{
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case OPd_f: // fcvt s31,d31
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cdb.gen1(INSTR.fcvt_float(1,4,V1,Vd));
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break;
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case OPf_d: // fcvt d31,s31
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cdb.gen1(INSTR.fcvt_float(0,5,V1,Vd));
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break;
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default:
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assert(0);
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}
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fixresult(cdb,e,retregs,pretregs);
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break;
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default:
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assert(0);
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}
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@ -1994,7 +1994,7 @@ void disassemble(uint c) @trusted
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field(ins,21,21) == 1 &&
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field(ins,14,10) == 0x10)
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{
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url = "floatdpl";
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url = "floatdp1";
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uint M = field(ins,31,31);
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uint S = field(ins,29,29);
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@ -718,9 +718,13 @@ struct INSTR
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static uint floatdp1(uint M, uint S, uint ftype, uint opcode, uint Rn, uint Rd)
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{
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assert(Rn < 32 && Rd < 32); // remember to convert R32-63 to 0-31
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return (M << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (0x10 << 10) | (Rn << 5) | Rd;
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return (M << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (opcode << 15) | (0x10 << 10) | (Rn << 5) | Rd;
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}
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/* FCVT fpreg,fpreg https://www.scs.stanford.edu/~zyedidia/arm64/fcvt_float.html
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*/
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static uint fcvt_float(uint ftype, uint opcode, reg_t Rn, reg_t Rd) { return floatdp1(0,0,ftype,opcode,Rn,Rd); }
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/* Floating-point compare
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* Floating-point immediate
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* Floating-point condistional compare
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