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add loaddata() fp support (#20877)

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Walter Bright 2025-02-16 03:47:19 -08:00 • committed by GitHub
parent 38c55096cd
commit 0131a00173
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GPG key ID: B5690EEEBB952194
3 changed files with 19 additions and 26 deletions
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37
compiler/src/dmd/backend/arm/cod1.d
View file

@ -2300,22 +2300,10 @@ static if (1)
cdrelconst(cgstate,cdb,e,outretregs);
return;
}
if (tyfloating(tym))
{
objmod.fltused();
if (config.fpxmmregs &&
(tym == TYcfloat || tym == TYcdouble) &&
(outretregs & (XMMREGS | mPSW))
)
{
cloadxmm(cdb, e, outretregs);
return;
}
}
if (outretregs == mPSW)
{
regm_t retregs = cgstate.allregs;
regm_t retregs = tyfloating(tym) ? INSTR.FLOATREGS : cgstate.allregs;
loaddata(cdb, e, retregs);
fixresult(cdb, e, retregs, outretregs);
return;
@ -2326,8 +2314,6 @@ static if (1)
cs.Iflags = 0;
flags = outretregs & mPSW; /* save original */
forregs = outretregs & (cgstate.allregs | INSTR.FLOATREGS); // XMMREGS ?
//if (outretregs & mSTACK)
//forregs |= DOUBLEREGS;
if (e.Eoper == OPconst)
{
if (tyvector(tym) && forregs & XMMREGS)
@ -2397,7 +2383,7 @@ static if (1)
const reg_t preg = e.Voffset ? e.Vsym.Spreg2 : e.Vsym.Spreg;
const regm_t pregm = mask(preg);
if (!(sz <= 2 && pregm & XMMREGS)) // no SIMD instructions to load 1 or 2 byte quantities
//if (!(sz <= 2 && pregm & XMMREGS)) // no SIMD instructions to load 1 or 2 byte quantities
{
if (debugr)
printf("%s.%d is fastpar and using register %s\n",
@ -2458,7 +2444,7 @@ static if (1)
}
}
}
else if (forregs & XMMREGS)
else if (0 && forregs & XMMREGS)
{
// Can't load from registers directly to XMM regs
//e.Vsym.Sflags &= ~GTregcand;
@ -2477,10 +2463,18 @@ static if (1)
}
else if (sz <= REGSIZE)
{
// LDR reg,[sp,#offset]
// https://www.scs.stanford.edu/~zyedidia/arm64/ldr_imm_gen.html
opcode_t opmv = PSOP.ldr | (29 << 5);
loadea(cdb, e, cs, opmv, reg, 0, 0, 0, RM.load);
if (tyfloating(tym))
{
loadea(cdb,e,cs,0,reg,0,0,0,RM.load);
outretregs = mask(reg);
}
else
{
// LDR reg,[sp,#offset]
// https://www.scs.stanford.edu/~zyedidia/arm64/ldr_imm_gen.html
opcode_t opmv = PSOP.ldr | (29 << 5);
loadea(cdb, e, cs, opmv, reg, 0, 0, 0, RM.load);
}
}
else if (sz <= 2 * REGSIZE)
{
@ -2515,6 +2509,7 @@ static if (1)
assert(0);
// Flags may already be set
outretregs &= flags | ~mPSW;
//printf("outretregs: %llx\n", outretregs);
fixresult(cdb, e, forregs, outretregs);
return;
}

6
compiler/src/dmd/backend/arm/cod4.d
View file

@ -893,10 +893,8 @@ void cdcmp(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
codelem(cgstate,cdb,e1,retregs1,1); // compute left leaf
regm_t retregs2 = INSTR.FLOATREGS & ~retregs1;
scodelem(cgstate,cdb,e2,retregs2,retregs1,true); // right leaf
reg_t Vm = 32;
//reg_t Vm = findreg(retregs1); // fix later, scodelem() isn't working
reg_t Vn = 33;
//reg_t Vn = findreg(retregs2); // fix later, scodelem() isn't working
reg_t Vm = findreg(retregs1);
reg_t Vn = findreg(retregs2);
uint ftype = INSTR.szToFtype(sz);
cdb.gen1(INSTR.fcmpe_float(ftype,Vm,Vn)); // FCMPE Vn,Vm
goto L3;

2
compiler/src/dmd/backend/arm/disasmarm.d
View file

@ -2048,7 +2048,7 @@ void disassemble(uint c) @trusted
{
p1 = opcode2 & 0x10 ? "fcmpe" : "fcmp";
p2 = fregString(rbuf[0..4],"sd h"[ftype],Rn);
p3 = Rm == 0 ? "#0.0" : fregString(rbuf[4..8],"sd h"[ftype],Rm);
p3 = (Rm == 0 && (opcode2 & 0x18) == 0x18) ? "#0.0" : fregString(rbuf[4..8],"sd h"[ftype],Rm);
}
}