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size_t was wrong, sign extension omitted (#21093)

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Walter Bright 2025-03-27 01:20:38 -07:00 • committed by GitHub
parent 653658faad
commit 001893d99c
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4 changed files with 12 additions and 4 deletions
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3
compiler/src/dmd/backend/arm/cod1.d
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@ -115,7 +115,8 @@ void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
cs.Iop = signExtend ? INSTR.ldrsh_imm(szw == 8, reg, cs.base, 0) cs.Iop = signExtend ? INSTR.ldrsh_imm(szw == 8, reg, cs.base, 0)
: INSTR.ldrh_imm (szw == 8, reg, cs.base, 0); : INSTR.ldrh_imm (szw == 8, reg, cs.base, 0);
else else
cs.Iop = INSTR.ldr_imm_gen(szw == 8, reg, cs.base, 0); cs.Iop = signExtend ? INSTR.ldrsw_imm(0, cs.base, reg)
: INSTR.ldr_imm_gen(szw == 8, reg, cs.base, 0);
} }
else else
assert(0); assert(0);

6
compiler/src/dmd/backend/arm/cod4.d
View file

@ -42,6 +42,7 @@ import dmd.backend.ty;
import dmd.backend.evalu8 : el_toldoubled; import dmd.backend.evalu8 : el_toldoubled;
import dmd.backend.x86.xmm; import dmd.backend.x86.xmm;
import dmd.backend.arm.cod1 : getlvalue, loadFromEA, storeToEA; import dmd.backend.arm.cod1 : getlvalue, loadFromEA, storeToEA;
import dmd.backend.arm.cod2 : tyToExtend;
import dmd.backend.arm.cod3 : COND, conditionCode, gentstreg; import dmd.backend.arm.cod3 : COND, conditionCode, gentstreg;
import dmd.backend.arm.instr; import dmd.backend.arm.instr;
@ -883,6 +884,7 @@ void cdcmp(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
/* See if we should reverse the comparison, so a JA => JC, and JBE => JNC /* See if we should reverse the comparison, so a JA => JC, and JBE => JNC
* (This is already reflected in the jop) * (This is already reflected in the jop)
*/ */
if (0)
if ((jop == COND.cs || jop == COND.cc) && if ((jop == COND.cs || jop == COND.cc) &&
(op == OPgt || op == OPle) && (op == OPgt || op == OPle) &&
(tyuns(tym) || tyuns(e2.Ety)) (tyuns(tym) || tyuns(e2.Ety))
@ -1599,7 +1601,7 @@ void cdshtlng(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
} }
else else
{ {
// BUG: not generating LDRSH // TODO AArch64: not generating LDRSH
loadFromEA(cs,reg,8,2); // LDRSH Xreg,[sp,#8] loadFromEA(cs,reg,8,2); // LDRSH Xreg,[sp,#8]
cdb.gen(&cs); cdb.gen(&cs);
} }
@ -1628,7 +1630,7 @@ void cdshtlng(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
} }
else else
{ {
// BUG: not generating LDRSW cs.Sextend = cast(ubyte)tyToExtend(TYint);
loadFromEA(cs,reg,8,4); // LDRSW Xreg,[sp,#8] loadFromEA(cs,reg,8,4); // LDRSW Xreg,[sp,#8]
cdb.gen(&cs); cdb.gen(&cs);
} }

5
compiler/src/dmd/backend/arm/instr.d
View file

@ -1004,6 +1004,11 @@ struct INSTR
return ldst_pos(size,1,opc,imm12,Rn,Vt); return ldst_pos(size,1,opc,imm12,Rn,Vt);
} }
/* https://www.scs.stanford.edu/~zyedidia/arm64/ldrsw_imm.html
* LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]
*/
static uint ldrsw_imm(uint imm12, reg_t Rn, reg_t Rt) { return ldst_pos(2,0,2,imm12,Rn,Rt); }
/* } */ /* } */
/* { ************************** Data Processing -- Register **********************************/ /* { ************************** Data Processing -- Register **********************************/

2
compiler/src/dmd/target.d
View file

@ -433,7 +433,7 @@ extern (C++) struct Target
DoubleProperties.initialize(); DoubleProperties.initialize();
RealProperties.initialize(); RealProperties.initialize();
isLP64 = isX86_64; isLP64 = isX86_64 || isAArch64;
// These have default values for 32 bit code, they get // These have default values for 32 bit code, they get
// adjusted for 64 bit code. // adjusted for 64 bit code.