582 lines
13 KiB
Raku
582 lines
13 KiB
Raku
#! /usr/bin/env perl
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# Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
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#
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# Licensed under the OpenSSL license (the "License"). You may not use
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# this file except in compliance with the License. You can obtain a copy
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# in the file LICENSE in the source distribution or at
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# https://www.openssl.org/source/license.html
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# March 2010
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#
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# The module implements "4-bit" GCM GHASH function and underlying
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# single multiplication operation in GF(2^128). "4-bit" means that it
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# uses 256 bytes per-key table [+128 bytes shared table]. Performance
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# results are for streamed GHASH subroutine on UltraSPARC pre-Tx CPU
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# and are expressed in cycles per processed byte, less is better:
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#
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# gcc 3.3.x cc 5.2 this assembler
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#
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# 32-bit build 81.4 43.3 12.6 (+546%/+244%)
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# 64-bit build 20.2 21.2 12.6 (+60%/+68%)
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#
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# Here is data collected on UltraSPARC T1 system running Linux:
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#
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# gcc 4.4.1 this assembler
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#
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# 32-bit build 566 50 (+1000%)
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# 64-bit build 56 50 (+12%)
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#
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# I don't quite understand why difference between 32-bit and 64-bit
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# compiler-generated code is so big. Compilers *were* instructed to
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# generate code for UltraSPARC and should have used 64-bit registers
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# for Z vector (see C code) even in 32-bit build... Oh well, it only
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# means more impressive improvement coefficients for this assembler
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# module;-) Loops are aggressively modulo-scheduled in respect to
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# references to input data and Z.hi updates to achieve 12 cycles
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# timing. To anchor to something else, sha1-sparcv9.pl spends 11.6
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# cycles to process one byte on UltraSPARC pre-Tx CPU and ~24 on T1.
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#
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# October 2012
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#
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# Add VIS3 lookup-table-free implementation using polynomial
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# multiplication xmulx[hi] and extended addition addxc[cc]
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# instructions. 4.52/7.63x improvement on T3/T4 or in absolute
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# terms 7.90/2.14 cycles per byte. On T4 multi-process benchmark
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# saturates at ~15.5x single-process result on 8-core processor,
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# or ~20.5GBps per 2.85GHz socket.
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$output=pop;
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open STDOUT,">$output";
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$frame="STACK_FRAME";
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$bias="STACK_BIAS";
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$Zhi="%o0"; # 64-bit values
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$Zlo="%o1";
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$Thi="%o2";
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$Tlo="%o3";
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$rem="%o4";
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$tmp="%o5";
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$nhi="%l0"; # small values and pointers
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$nlo="%l1";
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$xi0="%l2";
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$xi1="%l3";
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$rem_4bit="%l4";
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$remi="%l5";
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$Htblo="%l6";
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$cnt="%l7";
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$Xi="%i0"; # input argument block
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$Htbl="%i1";
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$inp="%i2";
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$len="%i3";
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$code.=<<___;
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#include "sparc_arch.h"
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#ifdef __arch64__
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.register %g2,#scratch
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.register %g3,#scratch
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#endif
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.section ".text",#alloc,#execinstr
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.align 64
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rem_4bit:
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.long `0x0000<<16`,0,`0x1C20<<16`,0,`0x3840<<16`,0,`0x2460<<16`,0
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.long `0x7080<<16`,0,`0x6CA0<<16`,0,`0x48C0<<16`,0,`0x54E0<<16`,0
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.long `0xE100<<16`,0,`0xFD20<<16`,0,`0xD940<<16`,0,`0xC560<<16`,0
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.long `0x9180<<16`,0,`0x8DA0<<16`,0,`0xA9C0<<16`,0,`0xB5E0<<16`,0
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.type rem_4bit,#object
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.size rem_4bit,(.-rem_4bit)
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.globl gcm_ghash_4bit
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.align 32
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gcm_ghash_4bit:
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save %sp,-$frame,%sp
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ldub [$inp+15],$nlo
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ldub [$Xi+15],$xi0
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ldub [$Xi+14],$xi1
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add $len,$inp,$len
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add $Htbl,8,$Htblo
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1: call .+8
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add %o7,rem_4bit-1b,$rem_4bit
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.Louter:
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xor $xi0,$nlo,$nlo
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and $nlo,0xf0,$nhi
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and $nlo,0x0f,$nlo
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sll $nlo,4,$nlo
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ldx [$Htblo+$nlo],$Zlo
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ldx [$Htbl+$nlo],$Zhi
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ldub [$inp+14],$nlo
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ldx [$Htblo+$nhi],$Tlo
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and $Zlo,0xf,$remi
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ldx [$Htbl+$nhi],$Thi
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sll $remi,3,$remi
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ldx [$rem_4bit+$remi],$rem
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srlx $Zlo,4,$Zlo
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mov 13,$cnt
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $xi1,$nlo,$nlo
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and $Zlo,0xf,$remi
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and $nlo,0xf0,$nhi
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and $nlo,0x0f,$nlo
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ba .Lghash_inner
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sll $nlo,4,$nlo
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.align 32
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.Lghash_inner:
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ldx [$Htblo+$nlo],$Tlo
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sll $remi,3,$remi
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xor $Thi,$Zhi,$Zhi
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ldx [$Htbl+$nlo],$Thi
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srlx $Zlo,4,$Zlo
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xor $rem,$Zhi,$Zhi
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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ldub [$inp+$cnt],$nlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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ldub [$Xi+$cnt],$xi1
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xor $Thi,$Zhi,$Zhi
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and $Zlo,0xf,$remi
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ldx [$Htblo+$nhi],$Tlo
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sll $remi,3,$remi
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xor $rem,$Zhi,$Zhi
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ldx [$Htbl+$nhi],$Thi
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srlx $Zlo,4,$Zlo
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $xi1,$nlo,$nlo
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srlx $Zhi,4,$Zhi
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and $nlo,0xf0,$nhi
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addcc $cnt,-1,$cnt
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xor $Zlo,$tmp,$Zlo
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and $nlo,0x0f,$nlo
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xor $Tlo,$Zlo,$Zlo
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sll $nlo,4,$nlo
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blu .Lghash_inner
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and $Zlo,0xf,$remi
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ldx [$Htblo+$nlo],$Tlo
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sll $remi,3,$remi
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xor $Thi,$Zhi,$Zhi
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ldx [$Htbl+$nlo],$Thi
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srlx $Zlo,4,$Zlo
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xor $rem,$Zhi,$Zhi
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $Thi,$Zhi,$Zhi
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add $inp,16,$inp
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cmp $inp,$len
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be,pn SIZE_T_CC,.Ldone
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and $Zlo,0xf,$remi
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ldx [$Htblo+$nhi],$Tlo
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sll $remi,3,$remi
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xor $rem,$Zhi,$Zhi
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ldx [$Htbl+$nhi],$Thi
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srlx $Zlo,4,$Zlo
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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ldub [$inp+15],$nlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $Thi,$Zhi,$Zhi
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stx $Zlo,[$Xi+8]
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xor $rem,$Zhi,$Zhi
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stx $Zhi,[$Xi]
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srl $Zlo,8,$xi1
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and $Zlo,0xff,$xi0
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ba .Louter
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and $xi1,0xff,$xi1
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.align 32
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.Ldone:
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ldx [$Htblo+$nhi],$Tlo
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sll $remi,3,$remi
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xor $rem,$Zhi,$Zhi
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ldx [$Htbl+$nhi],$Thi
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srlx $Zlo,4,$Zlo
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $Thi,$Zhi,$Zhi
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stx $Zlo,[$Xi+8]
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xor $rem,$Zhi,$Zhi
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stx $Zhi,[$Xi]
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ret
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restore
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.type gcm_ghash_4bit,#function
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.size gcm_ghash_4bit,(.-gcm_ghash_4bit)
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___
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undef $inp;
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undef $len;
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$code.=<<___;
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.globl gcm_gmult_4bit
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.align 32
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gcm_gmult_4bit:
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save %sp,-$frame,%sp
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ldub [$Xi+15],$nlo
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add $Htbl,8,$Htblo
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1: call .+8
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add %o7,rem_4bit-1b,$rem_4bit
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and $nlo,0xf0,$nhi
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and $nlo,0x0f,$nlo
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sll $nlo,4,$nlo
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ldx [$Htblo+$nlo],$Zlo
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ldx [$Htbl+$nlo],$Zhi
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ldub [$Xi+14],$nlo
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ldx [$Htblo+$nhi],$Tlo
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and $Zlo,0xf,$remi
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ldx [$Htbl+$nhi],$Thi
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sll $remi,3,$remi
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ldx [$rem_4bit+$remi],$rem
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srlx $Zlo,4,$Zlo
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mov 13,$cnt
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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and $Zlo,0xf,$remi
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and $nlo,0xf0,$nhi
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and $nlo,0x0f,$nlo
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ba .Lgmult_inner
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sll $nlo,4,$nlo
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.align 32
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.Lgmult_inner:
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ldx [$Htblo+$nlo],$Tlo
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sll $remi,3,$remi
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xor $Thi,$Zhi,$Zhi
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ldx [$Htbl+$nlo],$Thi
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srlx $Zlo,4,$Zlo
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xor $rem,$Zhi,$Zhi
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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ldub [$Xi+$cnt],$nlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $Thi,$Zhi,$Zhi
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and $Zlo,0xf,$remi
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ldx [$Htblo+$nhi],$Tlo
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sll $remi,3,$remi
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xor $rem,$Zhi,$Zhi
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ldx [$Htbl+$nhi],$Thi
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srlx $Zlo,4,$Zlo
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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srlx $Zhi,4,$Zhi
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and $nlo,0xf0,$nhi
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addcc $cnt,-1,$cnt
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xor $Zlo,$tmp,$Zlo
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and $nlo,0x0f,$nlo
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xor $Tlo,$Zlo,$Zlo
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sll $nlo,4,$nlo
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blu .Lgmult_inner
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and $Zlo,0xf,$remi
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ldx [$Htblo+$nlo],$Tlo
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sll $remi,3,$remi
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xor $Thi,$Zhi,$Zhi
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ldx [$Htbl+$nlo],$Thi
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srlx $Zlo,4,$Zlo
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xor $rem,$Zhi,$Zhi
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $Thi,$Zhi,$Zhi
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and $Zlo,0xf,$remi
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ldx [$Htblo+$nhi],$Tlo
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sll $remi,3,$remi
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xor $rem,$Zhi,$Zhi
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ldx [$Htbl+$nhi],$Thi
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srlx $Zlo,4,$Zlo
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ldx [$rem_4bit+$remi],$rem
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sllx $Zhi,60,$tmp
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xor $Tlo,$Zlo,$Zlo
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srlx $Zhi,4,$Zhi
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xor $Zlo,$tmp,$Zlo
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xor $Thi,$Zhi,$Zhi
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stx $Zlo,[$Xi+8]
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xor $rem,$Zhi,$Zhi
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stx $Zhi,[$Xi]
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ret
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restore
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.type gcm_gmult_4bit,#function
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.size gcm_gmult_4bit,(.-gcm_gmult_4bit)
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___
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{{{
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# Straightforward 128x128-bit multiplication using Karatsuba algorithm
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# followed by pair of 64-bit reductions [with a shortcut in first one,
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# which allowed to break dependency between reductions and remove one
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# multiplication from critical path]. While it might be suboptimal
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# with regard to sheer number of multiplications, other methods [such
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# as aggregate reduction] would require more 64-bit registers, which
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# we don't have in 32-bit application context.
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($Xip,$Htable,$inp,$len)=map("%i$_",(0..3));
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($Hhl,$Hlo,$Hhi,$Xlo,$Xhi,$xE1,$sqr, $C0,$C1,$C2,$C3,$V)=
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(map("%o$_",(0..5,7)),map("%g$_",(1..5)));
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($shl,$shr)=map("%l$_",(0..7));
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# For details regarding "twisted H" see ghash-x86.pl.
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$code.=<<___;
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.globl gcm_init_vis3
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.align 32
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gcm_init_vis3:
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save %sp,-$frame,%sp
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ldx [%i1+0],$Hhi
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ldx [%i1+8],$Hlo
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mov 0xE1,$Xhi
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mov 1,$Xlo
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sllx $Xhi,57,$Xhi
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srax $Hhi,63,$C0 ! broadcast carry
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addcc $Hlo,$Hlo,$Hlo ! H<<=1
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addxc $Hhi,$Hhi,$Hhi
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and $C0,$Xlo,$Xlo
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and $C0,$Xhi,$Xhi
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xor $Xlo,$Hlo,$Hlo
|
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xor $Xhi,$Hhi,$Hhi
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stx $Hlo,[%i0+8] ! save twisted H
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stx $Hhi,[%i0+0]
|
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|
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sethi %hi(0xA0406080),$V
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sethi %hi(0x20C0E000),%l0
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or $V,%lo(0xA0406080),$V
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or %l0,%lo(0x20C0E000),%l0
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sllx $V,32,$V
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or %l0,$V,$V ! (0xE0·i)&0xff=0xA040608020C0E000
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stx $V,[%i0+16]
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ret
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restore
|
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.type gcm_init_vis3,#function
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.size gcm_init_vis3,.-gcm_init_vis3
|
||
|
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.globl gcm_gmult_vis3
|
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.align 32
|
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gcm_gmult_vis3:
|
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save %sp,-$frame,%sp
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ldx [$Xip+8],$Xlo ! load Xi
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ldx [$Xip+0],$Xhi
|
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ldx [$Htable+8],$Hlo ! load twisted H
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ldx [$Htable+0],$Hhi
|
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|
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mov 0xE1,%l7
|
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sllx %l7,57,$xE1 ! 57 is not a typo
|
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ldx [$Htable+16],$V ! (0xE0·i)&0xff=0xA040608020C0E000
|
||
|
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xor $Hhi,$Hlo,$Hhl ! Karatsuba pre-processing
|
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xmulx $Xlo,$Hlo,$C0
|
||
xor $Xlo,$Xhi,$C2 ! Karatsuba pre-processing
|
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xmulx $C2,$Hhl,$C1
|
||
xmulxhi $Xlo,$Hlo,$Xlo
|
||
xmulxhi $C2,$Hhl,$C2
|
||
xmulxhi $Xhi,$Hhi,$C3
|
||
xmulx $Xhi,$Hhi,$Xhi
|
||
|
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sll $C0,3,$sqr
|
||
srlx $V,$sqr,$sqr ! ·0xE0 [implicit &(7<<3)]
|
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xor $C0,$sqr,$sqr
|
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sllx $sqr,57,$sqr ! ($C0·0xE1)<<1<<56 [implicit &0x7f]
|
||
|
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xor $C0,$C1,$C1 ! Karatsuba post-processing
|
||
xor $Xlo,$C2,$C2
|
||
xor $sqr,$Xlo,$Xlo ! real destination is $C1
|
||
xor $C3,$C2,$C2
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||
xor $Xlo,$C1,$C1
|
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xor $Xhi,$C2,$C2
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xor $Xhi,$C1,$C1
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|
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xmulxhi $C0,$xE1,$Xlo ! ·0xE1<<1<<56
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xor $C0,$C2,$C2
|
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xmulx $C1,$xE1,$C0
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xor $C1,$C3,$C3
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xmulxhi $C1,$xE1,$C1
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|
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xor $Xlo,$C2,$C2
|
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xor $C0,$C2,$C2
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xor $C1,$C3,$C3
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|
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stx $C2,[$Xip+8] ! save Xi
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||
stx $C3,[$Xip+0]
|
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|
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ret
|
||
restore
|
||
.type gcm_gmult_vis3,#function
|
||
.size gcm_gmult_vis3,.-gcm_gmult_vis3
|
||
|
||
.globl gcm_ghash_vis3
|
||
.align 32
|
||
gcm_ghash_vis3:
|
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save %sp,-$frame,%sp
|
||
nop
|
||
srln $len,0,$len ! needed on v8+, "nop" on v9
|
||
|
||
ldx [$Xip+8],$C2 ! load Xi
|
||
ldx [$Xip+0],$C3
|
||
ldx [$Htable+8],$Hlo ! load twisted H
|
||
ldx [$Htable+0],$Hhi
|
||
|
||
mov 0xE1,%l7
|
||
sllx %l7,57,$xE1 ! 57 is not a typo
|
||
ldx [$Htable+16],$V ! (0xE0·i)&0xff=0xA040608020C0E000
|
||
|
||
and $inp,7,$shl
|
||
andn $inp,7,$inp
|
||
sll $shl,3,$shl
|
||
prefetch [$inp+63], 20
|
||
sub %g0,$shl,$shr
|
||
|
||
xor $Hhi,$Hlo,$Hhl ! Karatsuba pre-processing
|
||
.Loop:
|
||
ldx [$inp+8],$Xlo
|
||
brz,pt $shl,1f
|
||
ldx [$inp+0],$Xhi
|
||
|
||
ldx [$inp+16],$C1 ! align data
|
||
srlx $Xlo,$shr,$C0
|
||
sllx $Xlo,$shl,$Xlo
|
||
sllx $Xhi,$shl,$Xhi
|
||
srlx $C1,$shr,$C1
|
||
or $C0,$Xhi,$Xhi
|
||
or $C1,$Xlo,$Xlo
|
||
1:
|
||
add $inp,16,$inp
|
||
sub $len,16,$len
|
||
xor $C2,$Xlo,$Xlo
|
||
xor $C3,$Xhi,$Xhi
|
||
prefetch [$inp+63], 20
|
||
|
||
xmulx $Xlo,$Hlo,$C0
|
||
xor $Xlo,$Xhi,$C2 ! Karatsuba pre-processing
|
||
xmulx $C2,$Hhl,$C1
|
||
xmulxhi $Xlo,$Hlo,$Xlo
|
||
xmulxhi $C2,$Hhl,$C2
|
||
xmulxhi $Xhi,$Hhi,$C3
|
||
xmulx $Xhi,$Hhi,$Xhi
|
||
|
||
sll $C0,3,$sqr
|
||
srlx $V,$sqr,$sqr ! ·0xE0 [implicit &(7<<3)]
|
||
xor $C0,$sqr,$sqr
|
||
sllx $sqr,57,$sqr ! ($C0·0xE1)<<1<<56 [implicit &0x7f]
|
||
|
||
xor $C0,$C1,$C1 ! Karatsuba post-processing
|
||
xor $Xlo,$C2,$C2
|
||
xor $sqr,$Xlo,$Xlo ! real destination is $C1
|
||
xor $C3,$C2,$C2
|
||
xor $Xlo,$C1,$C1
|
||
xor $Xhi,$C2,$C2
|
||
xor $Xhi,$C1,$C1
|
||
|
||
xmulxhi $C0,$xE1,$Xlo ! ·0xE1<<1<<56
|
||
xor $C0,$C2,$C2
|
||
xmulx $C1,$xE1,$C0
|
||
xor $C1,$C3,$C3
|
||
xmulxhi $C1,$xE1,$C1
|
||
|
||
xor $Xlo,$C2,$C2
|
||
xor $C0,$C2,$C2
|
||
brnz,pt $len,.Loop
|
||
xor $C1,$C3,$C3
|
||
|
||
stx $C2,[$Xip+8] ! save Xi
|
||
stx $C3,[$Xip+0]
|
||
|
||
ret
|
||
restore
|
||
.type gcm_ghash_vis3,#function
|
||
.size gcm_ghash_vis3,.-gcm_ghash_vis3
|
||
___
|
||
}}}
|
||
$code.=<<___;
|
||
.asciz "GHASH for SPARCv9/VIS3, CRYPTOGAMS by <appro\@openssl.org>"
|
||
.align 4
|
||
___
|
||
|
||
|
||
# Purpose of these subroutines is to explicitly encode VIS instructions,
|
||
# so that one can compile the module without having to specify VIS
|
||
# extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
|
||
# Idea is to reserve for option to produce "universal" binary and let
|
||
# programmer detect if current CPU is VIS capable at run-time.
|
||
sub unvis3 {
|
||
my ($mnemonic,$rs1,$rs2,$rd)=@_;
|
||
my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
|
||
my ($ref,$opf);
|
||
my %visopf = ( "addxc" => 0x011,
|
||
"addxccc" => 0x013,
|
||
"xmulx" => 0x115,
|
||
"xmulxhi" => 0x116 );
|
||
|
||
$ref = "$mnemonic\t$rs1,$rs2,$rd";
|
||
|
||
if ($opf=$visopf{$mnemonic}) {
|
||
foreach ($rs1,$rs2,$rd) {
|
||
return $ref if (!/%([goli])([0-9])/);
|
||
$_=$bias{$1}+$2;
|
||
}
|
||
|
||
return sprintf ".word\t0x%08x !%s",
|
||
0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
|
||
$ref;
|
||
} else {
|
||
return $ref;
|
||
}
|
||
}
|
||
|
||
foreach (split("\n",$code)) {
|
||
s/\`([^\`]*)\`/eval $1/ge;
|
||
|
||
s/\b(xmulx[hi]*|addxc[c]{0,2})\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
|
||
&unvis3($1,$2,$3,$4)
|
||
/ge;
|
||
|
||
print $_,"\n";
|
||
}
|
||
|
||
close STDOUT or die "error closing STDOUT: $!";
|