462 lines
10 KiB
Perl
462 lines
10 KiB
Perl
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#! /usr/bin/env perl
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# Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
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#
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# Licensed under the OpenSSL license (the "License"). You may not use
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# this file except in compliance with the License. You can obtain a copy
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# in the file LICENSE in the source distribution or at
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# https://www.openssl.org/source/license.html
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# SHA1 block procedure for MIPS.
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# Performance improvement is 30% on unaligned input. The "secret" is
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# to deploy lwl/lwr pair to load unaligned input. One could have
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# vectorized Xupdate on MIPSIII/IV, but the goal was to code MIPS32-
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# compatible subroutine. There is room for minor optimization on
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# little-endian platforms...
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# September 2012.
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#
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# Add MIPS32r2 code (>25% less instructions).
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######################################################################
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# There is a number of MIPS ABI in use, O32 and N32/64 are most
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# widely used. Then there is a new contender: NUBI. It appears that if
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# one picks the latter, it's possible to arrange code in ABI neutral
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# manner. Therefore let's stick to NUBI register layout:
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#
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($zero,$at,$t0,$t1,$t2)=map("\$$_",(0..2,24,25));
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($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
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($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));
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($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));
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#
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# The return value is placed in $a0. Following coding rules facilitate
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# interoperability:
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#
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# - never ever touch $tp, "thread pointer", former $gp;
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# - copy return value to $t0, former $v0 [or to $a0 if you're adapting
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# old code];
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# - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;
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#
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# For reference here is register layout for N32/64 MIPS ABIs:
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#
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# ($zero,$at,$v0,$v1)=map("\$$_",(0..3));
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# ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
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# ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25));
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# ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));
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# ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
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#
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$flavour = shift || "o32"; # supported flavours are o32,n32,64,nubi32,nubi64
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if ($flavour =~ /64|n32/i) {
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$PTR_ADD="daddu"; # incidentally works even on n32
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$PTR_SUB="dsubu"; # incidentally works even on n32
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$REG_S="sd";
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$REG_L="ld";
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$PTR_SLL="dsll"; # incidentally works even on n32
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$SZREG=8;
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} else {
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$PTR_ADD="addu";
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$PTR_SUB="subu";
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$REG_S="sw";
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$REG_L="lw";
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$PTR_SLL="sll";
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$SZREG=4;
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}
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#
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# <appro@openssl.org>
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#
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######################################################################
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$big_endian=(`echo MIPSEB | $ENV{CC} -E -`=~/MIPSEB/)?0:1 if ($ENV{CC});
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for (@ARGV) { $output=$_ if (/\w[\w\-]*\.\w+$/); }
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open STDOUT,">$output";
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if (!defined($big_endian))
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{ $big_endian=(unpack('L',pack('N',1))==1); }
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# offsets of the Most and Least Significant Bytes
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$MSB=$big_endian?0:3;
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$LSB=3&~$MSB;
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@X=map("\$$_",(8..23)); # a4-a7,s0-s11
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$ctx=$a0;
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$inp=$a1;
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$num=$a2;
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$A="\$1";
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$B="\$2";
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$C="\$3";
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$D="\$7";
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$E="\$24"; @V=($A,$B,$C,$D,$E);
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$t0="\$25";
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$t1=$num; # $num is offloaded to stack
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$t2="\$30"; # fp
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$K="\$31"; # ra
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sub BODY_00_14 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if (!$big_endian);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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wsbh @X[$i],@X[$i] # byte swap($i)
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rotr @X[$i],@X[$i],16
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#else
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srl $t0,@X[$i],24 # byte swap($i)
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srl $t1,@X[$i],8
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andi $t2,@X[$i],0xFF00
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sll @X[$i],@X[$i],24
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andi $t1,0xFF00
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sll $t2,$t2,8
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or @X[$i],$t0
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or $t1,$t2
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or @X[$i],$t1
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#endif
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___
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$code.=<<___;
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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addu $e,$K # $i
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xor $t0,$c,$d
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rotr $t1,$a,27
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and $t0,$b
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addu $e,$t1
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#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
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lw @X[$j],$j*4($inp)
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#else
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lwl @X[$j],$j*4+$MSB($inp)
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lwr @X[$j],$j*4+$LSB($inp)
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#endif
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xor $t0,$d
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addu $e,@X[$i]
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rotr $b,$b,2
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addu $e,$t0
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#else
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lwl @X[$j],$j*4+$MSB($inp)
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sll $t0,$a,5 # $i
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addu $e,$K
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lwr @X[$j],$j*4+$LSB($inp)
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srl $t1,$a,27
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addu $e,$t0
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xor $t0,$c,$d
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addu $e,$t1
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sll $t2,$b,30
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and $t0,$b
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srl $b,$b,2
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xor $t0,$d
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addu $e,@X[$i]
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or $b,$t2
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addu $e,$t0
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#endif
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___
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}
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sub BODY_15_19 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if (!$big_endian && $i==15);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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wsbh @X[$i],@X[$i] # byte swap($i)
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rotr @X[$i],@X[$i],16
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#else
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srl $t0,@X[$i],24 # byte swap($i)
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srl $t1,@X[$i],8
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andi $t2,@X[$i],0xFF00
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sll @X[$i],@X[$i],24
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andi $t1,0xFF00
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sll $t2,$t2,8
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or @X[$i],$t0
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or @X[$i],$t1
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or @X[$i],$t2
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#endif
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___
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$code.=<<___;
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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addu $e,$K # $i
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xor @X[$j%16],@X[($j+2)%16]
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xor $t0,$c,$d
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rotr $t1,$a,27
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xor @X[$j%16],@X[($j+8)%16]
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and $t0,$b
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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xor $t0,$d
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addu $e,@X[$i%16]
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rotr @X[$j%16],@X[$j%16],31
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rotr $b,$b,2
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addu $e,$t0
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#else
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xor @X[$j%16],@X[($j+2)%16]
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sll $t0,$a,5 # $i
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addu $e,$K
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srl $t1,$a,27
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addu $e,$t0
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xor @X[$j%16],@X[($j+8)%16]
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xor $t0,$c,$d
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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sll $t2,$b,30
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and $t0,$b
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srl $t1,@X[$j%16],31
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addu @X[$j%16],@X[$j%16]
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srl $b,$b,2
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xor $t0,$d
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or @X[$j%16],$t1
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addu $e,@X[$i%16]
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or $b,$t2
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addu $e,$t0
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#endif
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___
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}
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sub BODY_20_39 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if ($i<79);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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xor @X[$j%16],@X[($j+2)%16]
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addu $e,$K # $i
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rotr $t1,$a,27
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xor @X[$j%16],@X[($j+8)%16]
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xor $t0,$c,$d
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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xor $t0,$b
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addu $e,@X[$i%16]
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rotr @X[$j%16],@X[$j%16],31
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rotr $b,$b,2
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addu $e,$t0
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#else
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xor @X[$j%16],@X[($j+2)%16]
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sll $t0,$a,5 # $i
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addu $e,$K
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srl $t1,$a,27
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addu $e,$t0
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xor @X[$j%16],@X[($j+8)%16]
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xor $t0,$c,$d
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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sll $t2,$b,30
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xor $t0,$b
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srl $t1,@X[$j%16],31
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addu @X[$j%16],@X[$j%16]
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srl $b,$b,2
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addu $e,@X[$i%16]
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or @X[$j%16],$t1
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or $b,$t2
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addu $e,$t0
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#endif
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___
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$code.=<<___ if ($i==79);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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lw @X[0],0($ctx)
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addu $e,$K # $i
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lw @X[1],4($ctx)
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rotr $t1,$a,27
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lw @X[2],8($ctx)
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xor $t0,$c,$d
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addu $e,$t1
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lw @X[3],12($ctx)
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xor $t0,$b
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addu $e,@X[$i%16]
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lw @X[4],16($ctx)
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rotr $b,$b,2
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addu $e,$t0
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#else
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lw @X[0],0($ctx)
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sll $t0,$a,5 # $i
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addu $e,$K
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lw @X[1],4($ctx)
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srl $t1,$a,27
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addu $e,$t0
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lw @X[2],8($ctx)
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xor $t0,$c,$d
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addu $e,$t1
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lw @X[3],12($ctx)
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sll $t2,$b,30
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xor $t0,$b
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lw @X[4],16($ctx)
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srl $b,$b,2
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addu $e,@X[$i%16]
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or $b,$t2
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addu $e,$t0
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#endif
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___
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}
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sub BODY_40_59 {
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my ($i,$a,$b,$c,$d,$e)=@_;
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my $j=$i+1;
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$code.=<<___ if ($i<79);
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#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
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addu $e,$K # $i
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and $t0,$c,$d
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xor @X[$j%16],@X[($j+2)%16]
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rotr $t1,$a,27
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addu $e,$t0
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xor @X[$j%16],@X[($j+8)%16]
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xor $t0,$c,$d
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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and $t0,$b
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addu $e,@X[$i%16]
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rotr @X[$j%16],@X[$j%16],31
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rotr $b,$b,2
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addu $e,$t0
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#else
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xor @X[$j%16],@X[($j+2)%16]
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sll $t0,$a,5 # $i
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addu $e,$K
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srl $t1,$a,27
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addu $e,$t0
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xor @X[$j%16],@X[($j+8)%16]
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and $t0,$c,$d
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addu $e,$t1
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xor @X[$j%16],@X[($j+13)%16]
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sll $t2,$b,30
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addu $e,$t0
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srl $t1,@X[$j%16],31
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xor $t0,$c,$d
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addu @X[$j%16],@X[$j%16]
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and $t0,$b
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srl $b,$b,2
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or @X[$j%16],$t1
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addu $e,@X[$i%16]
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or $b,$t2
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addu $e,$t0
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#endif
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___
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}
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||
|
|
|
||
|
|
$FRAMESIZE=16; # large enough to accommodate NUBI saved registers
|
||
|
|
$SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";
|
||
|
|
|
||
|
|
$code=<<___;
|
||
|
|
#include "mips_arch.h"
|
||
|
|
|
||
|
|
.text
|
||
|
|
|
||
|
|
.set noat
|
||
|
|
.set noreorder
|
||
|
|
.align 5
|
||
|
|
.globl sha1_block_data_order
|
||
|
|
.ent sha1_block_data_order
|
||
|
|
sha1_block_data_order:
|
||
|
|
.frame $sp,$FRAMESIZE*$SZREG,$ra
|
||
|
|
.mask $SAVED_REGS_MASK,-$SZREG
|
||
|
|
.set noreorder
|
||
|
|
$PTR_SUB $sp,$FRAMESIZE*$SZREG
|
||
|
|
$REG_S $ra,($FRAMESIZE-1)*$SZREG($sp)
|
||
|
|
$REG_S $fp,($FRAMESIZE-2)*$SZREG($sp)
|
||
|
|
$REG_S $s11,($FRAMESIZE-3)*$SZREG($sp)
|
||
|
|
$REG_S $s10,($FRAMESIZE-4)*$SZREG($sp)
|
||
|
|
$REG_S $s9,($FRAMESIZE-5)*$SZREG($sp)
|
||
|
|
$REG_S $s8,($FRAMESIZE-6)*$SZREG($sp)
|
||
|
|
$REG_S $s7,($FRAMESIZE-7)*$SZREG($sp)
|
||
|
|
$REG_S $s6,($FRAMESIZE-8)*$SZREG($sp)
|
||
|
|
$REG_S $s5,($FRAMESIZE-9)*$SZREG($sp)
|
||
|
|
$REG_S $s4,($FRAMESIZE-10)*$SZREG($sp)
|
||
|
|
___
|
||
|
|
$code.=<<___ if ($flavour =~ /nubi/i); # optimize non-nubi prologue
|
||
|
|
$REG_S $s3,($FRAMESIZE-11)*$SZREG($sp)
|
||
|
|
$REG_S $s2,($FRAMESIZE-12)*$SZREG($sp)
|
||
|
|
$REG_S $s1,($FRAMESIZE-13)*$SZREG($sp)
|
||
|
|
$REG_S $s0,($FRAMESIZE-14)*$SZREG($sp)
|
||
|
|
$REG_S $gp,($FRAMESIZE-15)*$SZREG($sp)
|
||
|
|
___
|
||
|
|
$code.=<<___;
|
||
|
|
$PTR_SLL $num,6
|
||
|
|
$PTR_ADD $num,$inp
|
||
|
|
$REG_S $num,0($sp)
|
||
|
|
lw $A,0($ctx)
|
||
|
|
lw $B,4($ctx)
|
||
|
|
lw $C,8($ctx)
|
||
|
|
lw $D,12($ctx)
|
||
|
|
b .Loop
|
||
|
|
lw $E,16($ctx)
|
||
|
|
.align 4
|
||
|
|
.Loop:
|
||
|
|
.set reorder
|
||
|
|
#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
|
||
|
|
lui $K,0x5a82
|
||
|
|
lw @X[0],($inp)
|
||
|
|
ori $K,0x7999 # K_00_19
|
||
|
|
#else
|
||
|
|
lwl @X[0],$MSB($inp)
|
||
|
|
lui $K,0x5a82
|
||
|
|
lwr @X[0],$LSB($inp)
|
||
|
|
ori $K,0x7999 # K_00_19
|
||
|
|
#endif
|
||
|
|
___
|
||
|
|
for ($i=0;$i<15;$i++) { &BODY_00_14($i,@V); unshift(@V,pop(@V)); }
|
||
|
|
for (;$i<20;$i++) { &BODY_15_19($i,@V); unshift(@V,pop(@V)); }
|
||
|
|
$code.=<<___;
|
||
|
|
lui $K,0x6ed9
|
||
|
|
ori $K,0xeba1 # K_20_39
|
||
|
|
___
|
||
|
|
for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
|
||
|
|
$code.=<<___;
|
||
|
|
lui $K,0x8f1b
|
||
|
|
ori $K,0xbcdc # K_40_59
|
||
|
|
___
|
||
|
|
for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
|
||
|
|
$code.=<<___;
|
||
|
|
lui $K,0xca62
|
||
|
|
ori $K,0xc1d6 # K_60_79
|
||
|
|
___
|
||
|
|
for (;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
|
||
|
|
$code.=<<___;
|
||
|
|
$PTR_ADD $inp,64
|
||
|
|
$REG_L $num,0($sp)
|
||
|
|
|
||
|
|
addu $A,$X[0]
|
||
|
|
addu $B,$X[1]
|
||
|
|
sw $A,0($ctx)
|
||
|
|
addu $C,$X[2]
|
||
|
|
addu $D,$X[3]
|
||
|
|
sw $B,4($ctx)
|
||
|
|
addu $E,$X[4]
|
||
|
|
sw $C,8($ctx)
|
||
|
|
sw $D,12($ctx)
|
||
|
|
sw $E,16($ctx)
|
||
|
|
.set noreorder
|
||
|
|
bne $inp,$num,.Loop
|
||
|
|
nop
|
||
|
|
|
||
|
|
.set noreorder
|
||
|
|
$REG_L $ra,($FRAMESIZE-1)*$SZREG($sp)
|
||
|
|
$REG_L $fp,($FRAMESIZE-2)*$SZREG($sp)
|
||
|
|
$REG_L $s11,($FRAMESIZE-3)*$SZREG($sp)
|
||
|
|
$REG_L $s10,($FRAMESIZE-4)*$SZREG($sp)
|
||
|
|
$REG_L $s9,($FRAMESIZE-5)*$SZREG($sp)
|
||
|
|
$REG_L $s8,($FRAMESIZE-6)*$SZREG($sp)
|
||
|
|
$REG_L $s7,($FRAMESIZE-7)*$SZREG($sp)
|
||
|
|
$REG_L $s6,($FRAMESIZE-8)*$SZREG($sp)
|
||
|
|
$REG_L $s5,($FRAMESIZE-9)*$SZREG($sp)
|
||
|
|
$REG_L $s4,($FRAMESIZE-10)*$SZREG($sp)
|
||
|
|
___
|
||
|
|
$code.=<<___ if ($flavour =~ /nubi/i);
|
||
|
|
$REG_L $s3,($FRAMESIZE-11)*$SZREG($sp)
|
||
|
|
$REG_L $s2,($FRAMESIZE-12)*$SZREG($sp)
|
||
|
|
$REG_L $s1,($FRAMESIZE-13)*$SZREG($sp)
|
||
|
|
$REG_L $s0,($FRAMESIZE-14)*$SZREG($sp)
|
||
|
|
$REG_L $gp,($FRAMESIZE-15)*$SZREG($sp)
|
||
|
|
___
|
||
|
|
$code.=<<___;
|
||
|
|
jr $ra
|
||
|
|
$PTR_ADD $sp,$FRAMESIZE*$SZREG
|
||
|
|
.end sha1_block_data_order
|
||
|
|
.rdata
|
||
|
|
.asciiz "SHA1 for MIPS, CRYPTOGAMS by <appro\@openssl.org>"
|
||
|
|
___
|
||
|
|
print $code;
|
||
|
|
close STDOUT or die "error closing STDOUT: $!";
|