mirror of https://gitlab.com/basile.b/dexed.git
#97, add (physical) GPR setter
This commit is contained in:
Basile Burg
parent
2a1b430080
commit
095125a32b
116
src/ce_gdb.pas
116
src/ce_gdb.pas
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@ -7,7 +7,7 @@ interface
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uses
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Classes, SysUtils, FileUtil, Forms, Controls, Graphics, RegExpr, ComCtrls,
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PropEdits, GraphPropEdits, RTTIGrids, Dialogs, ExtCtrls, Menus, Buttons,
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StdCtrls, process, fpjson,
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StdCtrls, process, fpjson, typinfo,
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ce_common, ce_interfaces, ce_widget, ce_processes, ce_observer, ce_synmemo,
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ce_sharedres, ce_stringrange, ce_dsgncontrols, ce_dialogs, ce_dbgitf,
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ce_ddemangle, ce_writableComponent;
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@ -25,8 +25,7 @@ type
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TFpuRegister = (st0, st1, st2, st3, st4, st5, st6, st7);
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TFLAG = (CS, PF, AF, ZF, SF, TF, IF_, DF, OF_, NT, RF, VM,
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AC, VIF, VIP, ID);
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TFLAG = (CS, PF, AF, ZF, SF, TF, IF_, DF, OF_, NT, RF, VM, AC, VIF, VIP, ID);
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TEFLAG = set of TFLAG;
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TSegmentRegister = (S_CS, S_SS, S_DS, S_ES, S_FS, S_GS);
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@ -38,44 +37,50 @@ type
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TCpuRegValueEditor = class(TIntegerProperty)
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public
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function GetValue: ansistring; override;
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procedure SetValue(const NewValue: ansistring); override;
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end;
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TSetGprEvent = procedure(reg: TCpuRegister; val: TCpuRegValue) of object;
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// Makes a category for the general purpose registers in a project inspector
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TInspectableGPR = class(TPersistent)
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private
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fRegisters: array[TCpuRegister] of TCpuRegValue;
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fSetGprEvent: TSetGprEvent;
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procedure setRegister(index: TCpuRegister; value: TCpuRegValue);
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published
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{$IFDEF CPU64}
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property RAX: TCpuRegValue read fRegisters[TCpuRegister.rax];
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property RBX: TCpuRegValue read fRegisters[TCpuRegister.rbx];
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property RCX: TCpuRegValue read fRegisters[TCpuRegister.rcx];
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property RDX: TCpuRegValue read fRegisters[TCpuRegister.rdx];
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property RSI: TCpuRegValue read fRegisters[TCpuRegister.rsi];
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property RDI: TCpuRegValue read fRegisters[TCpuRegister.rdi];
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property RBP: TCpuRegValue read fRegisters[TCpuRegister.rbp];
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property RSP: TCpuRegValue read fRegisters[TCpuRegister.rsp];
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property R8: TCpuRegValue read fRegisters[TCpuRegister.r8];
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property R9: TCpuRegValue read fRegisters[TCpuRegister.r9];
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property R10: TCpuRegValue read fRegisters[TCpuRegister.r10];
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property R11: TCpuRegValue read fRegisters[TCpuRegister.r11];
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property R12: TCpuRegValue read fRegisters[TCpuRegister.r12];
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property R13: TCpuRegValue read fRegisters[TCpuRegister.r13];
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property R14: TCpuRegValue read fRegisters[TCpuRegister.r14];
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property R15: TCpuRegValue read fRegisters[TCpuRegister.r15];
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property RIP: TCpuRegValue read fRegisters[TCpuRegister.rip];
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property RAX: TCpuRegValue index TCpuRegister.rax read fRegisters[TCpuRegister.rax] write setRegister;
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property RBX: TCpuRegValue index TCpuRegister.rbx read fRegisters[TCpuRegister.rbx] write setRegister;
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property RCX: TCpuRegValue index TCpuRegister.rcx read fRegisters[TCpuRegister.rcx] write setRegister;
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property RDX: TCpuRegValue index TCpuRegister.rdx read fRegisters[TCpuRegister.rdx] write setRegister;
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property RSI: TCpuRegValue index TCpuRegister.rsi read fRegisters[TCpuRegister.rsi] write setRegister;
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property RDI: TCpuRegValue index TCpuRegister.rdi read fRegisters[TCpuRegister.rdi] write setRegister;
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property RBP: TCpuRegValue index TCpuRegister.rbp read fRegisters[TCpuRegister.rbp] write setRegister;
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property RSP: TCpuRegValue index TCpuRegister.rsp read fRegisters[TCpuRegister.rsp] write setRegister;
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property R8: TCpuRegValue index TCpuRegister.r8 read fRegisters[TCpuRegister.r8] write setRegister;
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property R9: TCpuRegValue index TCpuRegister.r9 read fRegisters[TCpuRegister.r9] write setRegister;
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property R10: TCpuRegValue index TCpuRegister.r10 read fRegisters[TCpuRegister.r10] write setRegister;
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property R11: TCpuRegValue index TCpuRegister.r11 read fRegisters[TCpuRegister.r11] write setRegister;
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property R12: TCpuRegValue index TCpuRegister.r12 read fRegisters[TCpuRegister.r12] write setRegister;
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property R13: TCpuRegValue index TCpuRegister.r13 read fRegisters[TCpuRegister.r13] write setRegister;
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property R14: TCpuRegValue index TCpuRegister.r14 read fRegisters[TCpuRegister.r14] write setRegister;
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property R15: TCpuRegValue index TCpuRegister.r15 read fRegisters[TCpuRegister.r15] write setRegister;
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property RIP: TCpuRegValue index TCpuRegister.rip read fRegisters[TCpuRegister.rip] write setRegister;
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{$ELSE}
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property EAX: TCpuRegValue read fRegisters[TCpuRegister.eax];
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property EBX: TCpuRegValue read fRegisters[TCpuRegister.ebx];
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property ECX: TCpuRegValue read fRegisters[TCpuRegister.ecx];
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property EDX: TCpuRegValue read fRegisters[TCpuRegister.edx];
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property ESI: TCpuRegValue read fRegisters[TCpuRegister.esi];
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property EDI: TCpuRegValue read fRegisters[TCpuRegister.edi];
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property EBP: TCpuRegValue read fRegisters[TCpuRegister.ebp];
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property ESP: TCpuRegValue read fRegisters[TCpuRegister.esp];
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property EIP: TCpuRegValue read fRegisters[TCpuRegister.eip];
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property EAX: TCpuRegValue index TCpuRegister.eax read fRegisters[TCpuRegister.eax] write setRegister;
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property EBX: TCpuRegValue index TCpuRegister.ebx read fRegisters[TCpuRegister.ebx] write setRegister;
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property ECX: TCpuRegValue index TCpuRegister.ecx read fRegisters[TCpuRegister.ecx] write setRegister;
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property EDX: TCpuRegValue index TCpuRegister.edx read fRegisters[TCpuRegister.edx] write setRegister;
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property ESI: TCpuRegValue index TCpuRegister.esi read fRegisters[TCpuRegister.esi] write setRegister;
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property EDI: TCpuRegValue index TCpuRegister.edi read fRegisters[TCpuRegister.edi] write setRegister;
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property EBP: TCpuRegValue index TCpuRegister.ebp read fRegisters[TCpuRegister.ebp] write setRegister;
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property ESP: TCpuRegValue index TCpuRegister.esp read fRegisters[TCpuRegister.esp] write setRegister;
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property EIP: TCpuRegValue index TCpuRegister.eip read fRegisters[TCpuRegister.eip] write setRegister;
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{$ENDIF}
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public
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procedure setRegister(index: TCpuRegister; value: PtrUInt);
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constructor create(event: TSetGprEvent);
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procedure setInspectableRegister(index: TCpuRegister; value: PtrUInt);
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end;
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// Makes a category for the floating point coprocessor registers in a project inspector
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@ -92,7 +97,7 @@ type
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property ST6: double read fRegisters[TFpuRegister.st6];
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property ST7: double read fRegisters[TFpuRegister.st7];
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public
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procedure setRegister(index: TFpuRegister; value: double);
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procedure setInspectableRegister(index: TFpuRegister; value: double);
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end;
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// Makes a category for the SSE registers in a project inspector
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@ -120,7 +125,7 @@ type
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property GS: byte read fSegment[TSegmentRegister.S_GS];
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property SS: byte read fSegment[TSegmentRegister.S_SS];
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public
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constructor create;
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constructor create(setGprEvent: TSetGprEvent);
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destructor destroy; override;
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end;
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@ -251,6 +256,7 @@ type
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procedure infoRegs;
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procedure infoStack;
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procedure sendCustomCommand;
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procedure setGpr(reg: TCpuRegister; val: TCpuRegValue);
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//
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procedure projNew(project: ICECommonProject);
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procedure projChanged(project: ICECommonProject);
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@ -479,19 +485,42 @@ begin
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{$ENDIF}
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end;
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procedure TInspectableGPR.setRegister(index: TCpuRegister; value: PtrUInt);
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procedure TCpuRegValueEditor.SetValue(const NewValue: ansistring);
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begin
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try
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{$IFDEF CPU64}
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SetInt64Value(StrToQWord(NewValue));
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{$ELSE}
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SetOrdValue(StrToInt(NewValue));
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{$ENDIF}
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except
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end;
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end;
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constructor TInspectableGPR.create(event: TSetGprEvent);
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begin
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fSetGprEvent:=event;
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end;
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procedure TInspectableGPR.setInspectableRegister(index: TCpuRegister; value: PtrUInt);
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begin
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fRegisters[index] := value;
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end;
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procedure TInspectableFPR.setRegister(index: TFpuRegister; value: double);
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procedure TInspectableGPR.setRegister(index: TCpuRegister; value: TCpuRegValue);
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begin
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fSetGprEvent(index, value);
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fRegisters[index] := value;
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end;
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procedure TInspectableFPR.setInspectableRegister(index: TFpuRegister; value: double);
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begin
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fRegisters[index] := value;
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end;
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constructor TInspectableState.create;
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constructor TInspectableState.create(setGprEvent: TSetGprEvent);
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begin
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fGpr := TInspectableGPR.Create;
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fGpr := TInspectableGPR.Create(setGprEvent);
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end;
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destructor TInspectableState.destroy;
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@ -511,7 +540,7 @@ begin
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fMsg:= getMessageDisplay;
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fFileLineBrks:= TStringList.Create;
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fLog := TStringList.Create;
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fInspState := TInspectableState.Create;
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fInspState := TInspectableState.Create(@setGpr);
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stateViewer.TIObject := fInspState;
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fJson := TJsonObject.Create;
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fStackItems := TStackItems.create;
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@ -1032,7 +1061,7 @@ begin
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if val.isNotNil then
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begin
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if (0 <= number) and (TCpuRegister(number) <= high(TCpuRegister)) then
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fInspState.CPU.setRegister(TCpuRegister(number),
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fInspState.CPU.setInspectableRegister(TCpuRegister(number),
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{$IFDEF CPU64}val.AsInt64{$ELSE}val.AsInteger{$ENDIF});
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end;
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@ -1212,6 +1241,17 @@ begin
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edit1.Items.Add(cmd);
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edit1.Text := '';
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end;
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procedure TCEGdbWidget.setGpr(reg: TCpuRegister; val: TCpuRegValue);
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const
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spec = 'set $%s = 0x%X';
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var
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cmd : string;
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begin
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cmd := format(spec, [GetEnumName(typeinfo(TCpuRegister),integer(reg)), val]);
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gdbCommand(cmd);
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end;
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{$ENDREGION}
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initialization
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