405 lines
12 KiB
C
405 lines
12 KiB
C
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/*
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* Copyright (c) 2003, 2007-14 Matteo Frigo
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* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#if defined(FFTW_LDOUBLE) || defined(FFTW_QUAD)
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#error "AVX only works in single or double precision"
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#endif
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#ifdef FFTW_SINGLE
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# define DS(d,s) s /* single-precision option */
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# define SUFF(name) name ## s
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#else
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# define DS(d,s) d /* double-precision option */
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# define SUFF(name) name ## d
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#endif
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#define SIMD_SUFFIX _avx /* for renaming */
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#define VL DS(2, 4) /* SIMD complex vector length */
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#define SIMD_VSTRIDE_OKA(x) ((x) == 2)
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#define SIMD_STRIDE_OKPAIR SIMD_STRIDE_OK
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#if defined(__GNUC__) && !defined(__AVX__) /* sanity check */
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#error "compiling simd-avx.h without -mavx"
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#endif
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#ifdef _MSC_VER
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#ifndef inline
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#define inline __inline
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#endif
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#endif
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#include <immintrin.h>
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typedef DS(__m256d, __m256) V;
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#define VADD SUFF(_mm256_add_p)
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#define VSUB SUFF(_mm256_sub_p)
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#define VMUL SUFF(_mm256_mul_p)
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#define VXOR SUFF(_mm256_xor_p)
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#define VSHUF SUFF(_mm256_shuffle_p)
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#define SHUFVALD(fp0,fp1) \
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(((fp1) << 3) | ((fp0) << 2) | ((fp1) << 1) | ((fp0)))
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#define SHUFVALS(fp0,fp1,fp2,fp3) \
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(((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | ((fp0)))
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#define VDUPL(x) DS(_mm256_unpacklo_pd(x, x), VSHUF(x, x, SHUFVALS(0, 0, 2, 2)))
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#define VDUPH(x) DS(_mm256_unpackhi_pd(x, x), VSHUF(x, x, SHUFVALS(1, 1, 3, 3)))
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#define VLIT(x0, x1) DS(_mm256_set_pd(x0, x1, x0, x1), _mm256_set_ps(x0, x1, x0, x1, x0, x1, x0, x1))
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#define DVK(var, val) V var = VLIT(val, val)
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#define LDK(x) x
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static inline V LDA(const R *x, INT ivs, const R *aligned_like)
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{
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(void)aligned_like; /* UNUSED */
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(void)ivs; /* UNUSED */
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return SUFF(_mm256_loadu_p)(x);
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}
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static inline void STA(R *x, V v, INT ovs, const R *aligned_like)
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{
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(void)aligned_like; /* UNUSED */
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(void)ovs; /* UNUSED */
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SUFF(_mm256_storeu_p)(x, v);
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}
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#if FFTW_SINGLE
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# ifdef _MSC_VER
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/* Temporarily disable the warning "uninitialized local variable
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'name' used" and runtime checks for using a variable before it is
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defined which is erroneously triggered by the LOADL0 / LOADH macros
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as they only modify VAL partly each. */
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# ifndef __INTEL_COMPILER
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# pragma warning(disable : 4700)
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# pragma runtime_checks("u", off)
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# endif
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# endif
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# ifdef __INTEL_COMPILER
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# pragma warning(disable : 592)
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# endif
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#define LOADH(addr, val) _mm_loadh_pi(val, (const __m64 *)(addr))
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#define LOADL(addr, val) _mm_loadl_pi(val, (const __m64 *)(addr))
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#define STOREH(addr, val) _mm_storeh_pi((__m64 *)(addr), val)
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#define STOREL(addr, val) _mm_storel_pi((__m64 *)(addr), val)
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/* it seems like the only AVX way to store 4 complex floats is to
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extract two pairs of complex floats into two __m128 registers, and
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then use SSE-like half-stores. Similarly, to load 4 complex
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floats, we load two pairs of complex floats into two __m128
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registers, and then pack the two __m128 registers into one __m256
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value. */
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static inline V LD(const R *x, INT ivs, const R *aligned_like)
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{
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__m128 l, h;
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V v;
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(void)aligned_like; /* UNUSED */
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l = LOADL(x, l);
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l = LOADH(x + ivs, l);
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h = LOADL(x + 2*ivs, h);
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h = LOADH(x + 3*ivs, h);
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v = _mm256_castps128_ps256(l);
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v = _mm256_insertf128_ps(v, h, 1);
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return v;
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}
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# ifdef _MSC_VER
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# ifndef __INTEL_COMPILER
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# pragma warning(default : 4700)
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# pragma runtime_checks("u", restore)
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# endif
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# endif
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# ifdef __INTEL_COMPILER
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# pragma warning(default : 592)
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# endif
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static inline void ST(R *x, V v, INT ovs, const R *aligned_like)
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{
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__m128 h = _mm256_extractf128_ps(v, 1);
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__m128 l = _mm256_castps256_ps128(v);
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(void)aligned_like; /* UNUSED */
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/* WARNING: the extra_iter hack depends upon STOREL occurring
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after STOREH */
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STOREH(x + 3*ovs, h);
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STOREL(x + 2*ovs, h);
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STOREH(x + ovs, l);
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STOREL(x, l);
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}
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#define STM2(x, v, ovs, aligned_like) /* no-op */
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static inline void STN2(R *x, V v0, V v1, INT ovs)
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{
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V x0 = VSHUF(v0, v1, SHUFVALS(0, 1, 0, 1));
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V x1 = VSHUF(v0, v1, SHUFVALS(2, 3, 2, 3));
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__m128 h0 = _mm256_extractf128_ps(x0, 1);
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__m128 l0 = _mm256_castps256_ps128(x0);
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__m128 h1 = _mm256_extractf128_ps(x1, 1);
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__m128 l1 = _mm256_castps256_ps128(x1);
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*(__m128 *)(x + 3*ovs) = h1;
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*(__m128 *)(x + 2*ovs) = h0;
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*(__m128 *)(x + 1*ovs) = l1;
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*(__m128 *)(x + 0*ovs) = l0;
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}
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#define STM4(x, v, ovs, aligned_like) /* no-op */
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#define STN4(x, v0, v1, v2, v3, ovs) \
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{ \
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V xxx0, xxx1, xxx2, xxx3; \
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V yyy0, yyy1, yyy2, yyy3; \
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xxx0 = _mm256_unpacklo_ps(v0, v2); \
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xxx1 = _mm256_unpackhi_ps(v0, v2); \
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xxx2 = _mm256_unpacklo_ps(v1, v3); \
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xxx3 = _mm256_unpackhi_ps(v1, v3); \
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yyy0 = _mm256_unpacklo_ps(xxx0, xxx2); \
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yyy1 = _mm256_unpackhi_ps(xxx0, xxx2); \
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yyy2 = _mm256_unpacklo_ps(xxx1, xxx3); \
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yyy3 = _mm256_unpackhi_ps(xxx1, xxx3); \
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*(__m128 *)(x + 0 * ovs) = _mm256_castps256_ps128(yyy0); \
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*(__m128 *)(x + 4 * ovs) = _mm256_extractf128_ps(yyy0, 1); \
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*(__m128 *)(x + 1 * ovs) = _mm256_castps256_ps128(yyy1); \
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*(__m128 *)(x + 5 * ovs) = _mm256_extractf128_ps(yyy1, 1); \
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*(__m128 *)(x + 2 * ovs) = _mm256_castps256_ps128(yyy2); \
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*(__m128 *)(x + 6 * ovs) = _mm256_extractf128_ps(yyy2, 1); \
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*(__m128 *)(x + 3 * ovs) = _mm256_castps256_ps128(yyy3); \
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*(__m128 *)(x + 7 * ovs) = _mm256_extractf128_ps(yyy3, 1); \
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}
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#else
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static inline __m128d VMOVAPD_LD(const R *x)
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{
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/* gcc-4.6 miscompiles the combination _mm256_castpd128_pd256(VMOVAPD_LD(x))
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into a 256-bit vmovapd, which requires 32-byte aligment instead of
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16-byte alignment.
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Force the use of vmovapd via asm until compilers stabilize.
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*/
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#if defined(__GNUC__)
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__m128d var;
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__asm__("vmovapd %1, %0\n" : "=x"(var) : "m"(x[0]));
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return var;
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#else
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return *(const __m128d *)x;
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#endif
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}
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static inline V LD(const R *x, INT ivs, const R *aligned_like)
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{
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V var;
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(void)aligned_like; /* UNUSED */
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var = _mm256_castpd128_pd256(VMOVAPD_LD(x));
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var = _mm256_insertf128_pd(var, *(const __m128d *)(x+ivs), 1);
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return var;
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}
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static inline void ST(R *x, V v, INT ovs, const R *aligned_like)
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{
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(void)aligned_like; /* UNUSED */
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/* WARNING: the extra_iter hack depends upon the store of the low
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part occurring after the store of the high part */
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*(__m128d *)(x + ovs) = _mm256_extractf128_pd(v, 1);
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*(__m128d *)x = _mm256_castpd256_pd128(v);
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}
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#define STM2 ST
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#define STN2(x, v0, v1, ovs) /* nop */
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#define STM4(x, v, ovs, aligned_like) /* no-op */
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/* STN4 is a macro, not a function, thanks to Visual C++ developers
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deciding "it would be infrequent that people would want to pass more
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than 3 [__m128 parameters] by value." Even though the comment
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was made about __m128 parameters, it appears to apply to __m256
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parameters as well. */
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#define STN4(x, v0, v1, v2, v3, ovs) \
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{ \
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V xxx0, xxx1, xxx2, xxx3; \
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xxx0 = _mm256_unpacklo_pd(v0, v1); \
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xxx1 = _mm256_unpackhi_pd(v0, v1); \
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xxx2 = _mm256_unpacklo_pd(v2, v3); \
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xxx3 = _mm256_unpackhi_pd(v2, v3); \
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STA(x, _mm256_permute2f128_pd(xxx0, xxx2, 0x20), 0, 0); \
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STA(x + ovs, _mm256_permute2f128_pd(xxx1, xxx3, 0x20), 0, 0); \
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STA(x + 2 * ovs, _mm256_permute2f128_pd(xxx0, xxx2, 0x31), 0, 0); \
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STA(x + 3 * ovs, _mm256_permute2f128_pd(xxx1, xxx3, 0x31), 0, 0); \
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}
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#endif
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static inline V FLIP_RI(V x)
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{
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return VSHUF(x, x,
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DS(SHUFVALD(1, 0),
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SHUFVALS(1, 0, 3, 2)));
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}
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static inline V VCONJ(V x)
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{
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/* Produce a SIMD vector[VL] of (0 + -0i).
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We really want to write this:
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V pmpm = VLIT(-0.0, 0.0);
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but historically some compilers have ignored the distiction
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between +0 and -0. It looks like 'gcc-8 -fast-math' treats -0
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as 0 too.
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*/
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union uvec {
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unsigned u[8];
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V v;
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};
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static const union uvec pmpm = {
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#ifdef FFTW_SINGLE
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{ 0x00000000, 0x80000000, 0x00000000, 0x80000000,
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0x00000000, 0x80000000, 0x00000000, 0x80000000 }
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#else
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{ 0x00000000, 0x00000000, 0x00000000, 0x80000000,
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0x00000000, 0x00000000, 0x00000000, 0x80000000 }
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#endif
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};
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return VXOR(pmpm.v, x);
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}
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static inline V VBYI(V x)
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{
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return FLIP_RI(VCONJ(x));
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}
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/* FMA support */
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#define VFMA(a, b, c) VADD(c, VMUL(a, b))
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#define VFNMS(a, b, c) VSUB(c, VMUL(a, b))
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#define VFMS(a, b, c) VSUB(VMUL(a, b), c)
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#define VFMAI(b, c) VADD(c, VBYI(b))
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#define VFNMSI(b, c) VSUB(c, VBYI(b))
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#define VFMACONJ(b,c) VADD(VCONJ(b),c)
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#define VFMSCONJ(b,c) VSUB(VCONJ(b),c)
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#define VFNMSCONJ(b,c) VSUB(c, VCONJ(b))
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static inline V VZMUL(V tx, V sr)
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{
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V tr = VDUPL(tx);
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V ti = VDUPH(tx);
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tr = VMUL(sr, tr);
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sr = VBYI(sr);
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return VFMA(ti, sr, tr);
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}
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static inline V VZMULJ(V tx, V sr)
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{
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V tr = VDUPL(tx);
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V ti = VDUPH(tx);
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tr = VMUL(sr, tr);
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sr = VBYI(sr);
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return VFNMS(ti, sr, tr);
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}
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static inline V VZMULI(V tx, V sr)
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{
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V tr = VDUPL(tx);
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V ti = VDUPH(tx);
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ti = VMUL(ti, sr);
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sr = VBYI(sr);
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return VFMS(tr, sr, ti);
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}
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static inline V VZMULIJ(V tx, V sr)
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{
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V tr = VDUPL(tx);
|
||
|
|
V ti = VDUPH(tx);
|
||
|
|
ti = VMUL(ti, sr);
|
||
|
|
sr = VBYI(sr);
|
||
|
|
return VFMA(tr, sr, ti);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* twiddle storage #1: compact, slower */
|
||
|
|
#ifdef FFTW_SINGLE
|
||
|
|
# define VTW1(v,x) {TW_CEXP, v, x}, {TW_CEXP, v+1, x}, {TW_CEXP, v+2, x}, {TW_CEXP, v+3, x}
|
||
|
|
#else
|
||
|
|
# define VTW1(v,x) {TW_CEXP, v, x}, {TW_CEXP, v+1, x}
|
||
|
|
#endif
|
||
|
|
#define TWVL1 (VL)
|
||
|
|
|
||
|
|
static inline V BYTW1(const R *t, V sr)
|
||
|
|
{
|
||
|
|
return VZMUL(LDA(t, 2, t), sr);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline V BYTWJ1(const R *t, V sr)
|
||
|
|
{
|
||
|
|
return VZMULJ(LDA(t, 2, t), sr);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* twiddle storage #2: twice the space, faster (when in cache) */
|
||
|
|
#ifdef FFTW_SINGLE
|
||
|
|
# define VTW2(v,x) \
|
||
|
|
{TW_COS, v, x}, {TW_COS, v, x}, {TW_COS, v+1, x}, {TW_COS, v+1, x}, \
|
||
|
|
{TW_COS, v+2, x}, {TW_COS, v+2, x}, {TW_COS, v+3, x}, {TW_COS, v+3, x}, \
|
||
|
|
{TW_SIN, v, -x}, {TW_SIN, v, x}, {TW_SIN, v+1, -x}, {TW_SIN, v+1, x}, \
|
||
|
|
{TW_SIN, v+2, -x}, {TW_SIN, v+2, x}, {TW_SIN, v+3, -x}, {TW_SIN, v+3, x}
|
||
|
|
#else
|
||
|
|
# define VTW2(v,x) \
|
||
|
|
{TW_COS, v, x}, {TW_COS, v, x}, {TW_COS, v+1, x}, {TW_COS, v+1, x}, \
|
||
|
|
{TW_SIN, v, -x}, {TW_SIN, v, x}, {TW_SIN, v+1, -x}, {TW_SIN, v+1, x}
|
||
|
|
#endif
|
||
|
|
#define TWVL2 (2 * VL)
|
||
|
|
|
||
|
|
static inline V BYTW2(const R *t, V sr)
|
||
|
|
{
|
||
|
|
const V *twp = (const V *)t;
|
||
|
|
V si = FLIP_RI(sr);
|
||
|
|
V tr = twp[0], ti = twp[1];
|
||
|
|
return VFMA(tr, sr, VMUL(ti, si));
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline V BYTWJ2(const R *t, V sr)
|
||
|
|
{
|
||
|
|
const V *twp = (const V *)t;
|
||
|
|
V si = FLIP_RI(sr);
|
||
|
|
V tr = twp[0], ti = twp[1];
|
||
|
|
return VFNMS(ti, si, VMUL(tr, sr));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* twiddle storage #3 */
|
||
|
|
#define VTW3 VTW1
|
||
|
|
#define TWVL3 TWVL1
|
||
|
|
|
||
|
|
/* twiddle storage for split arrays */
|
||
|
|
#ifdef FFTW_SINGLE
|
||
|
|
# define VTWS(v,x) \
|
||
|
|
{TW_COS, v, x}, {TW_COS, v+1, x}, {TW_COS, v+2, x}, {TW_COS, v+3, x}, \
|
||
|
|
{TW_COS, v+4, x}, {TW_COS, v+5, x}, {TW_COS, v+6, x}, {TW_COS, v+7, x}, \
|
||
|
|
{TW_SIN, v, x}, {TW_SIN, v+1, x}, {TW_SIN, v+2, x}, {TW_SIN, v+3, x}, \
|
||
|
|
{TW_SIN, v+4, x}, {TW_SIN, v+5, x}, {TW_SIN, v+6, x}, {TW_SIN, v+7, x}
|
||
|
|
#else
|
||
|
|
# define VTWS(v,x) \
|
||
|
|
{TW_COS, v, x}, {TW_COS, v+1, x}, {TW_COS, v+2, x}, {TW_COS, v+3, x}, \
|
||
|
|
{TW_SIN, v, x}, {TW_SIN, v+1, x}, {TW_SIN, v+2, x}, {TW_SIN, v+3, x}
|
||
|
|
#endif
|
||
|
|
#define TWVLS (2 * VL)
|
||
|
|
|
||
|
|
|
||
|
|
/* Use VZEROUPPER to avoid the penalty of switching from AVX to SSE.
|
||
|
|
See Intel Optimization Manual (April 2011, version 248966), Section
|
||
|
|
11.3 */
|
||
|
|
#define VLEAVE _mm256_zeroupper
|
||
|
|
|
||
|
|
#include "simd-common.h"
|